| /freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/ |
| H A D | RISCVTargetParser.h | 52 enum VLMUL : uint8_t { enum
81 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
84 inline static RISCVII::VLMUL getVLMUL(unsigned VType) { in getVLMUL()
85 unsigned VLMUL = VType & 0x7; in getVLMUL() local
86 return static_cast<RISCVII::VLMUL>(VLMUL); in getVLMUL()
90 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
92 inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) { in encodeLMUL()
95 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2); in encodeLMUL()
119 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
121 std::optional<RISCVII::VLMUL>
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | RISCVTargetParser.cpp | 159 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, in encodeVTYPE() argument
162 unsigned VLMULBits = static_cast<unsigned>(VLMUL); in encodeVTYPE()
173 std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL) { in decodeVLMUL() argument
174 switch (VLMUL) { in decodeVLMUL()
177 case RISCVII::VLMUL::LMUL_1: in decodeVLMUL()
178 case RISCVII::VLMUL::LMUL_2: in decodeVLMUL()
179 case RISCVII::VLMUL::LMUL_4: in decodeVLMUL()
180 case RISCVII::VLMUL::LMUL_8: in decodeVLMUL()
181 return std::make_pair(1 << static_cast<unsigned>(VLMUL), false); in decodeVLMUL()
182 case RISCVII::VLMUL::LMUL_F2: in decodeVLMUL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 110 RISCVII::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI); in createInstruments() local
113 switch (VLMUL) { in createInstruments()
169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL()
252 RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(LMUL); in getSchedClassID() local
253 auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW); in getSchedClassID()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 240 unsigned NF, RISCVII::VLMUL LMUL) { in createTuple()
256 case RISCVII::VLMUL::LMUL_F8: in createTuple()
257 case RISCVII::VLMUL::LMUL_F4: in createTuple()
258 case RISCVII::VLMUL::LMUL_F2: in createTuple()
259 case RISCVII::VLMUL::LMUL_1: in createTuple()
265 case RISCVII::VLMUL::LMUL_2: in createTuple()
271 case RISCVII::VLMUL::LMUL_4: in createTuple()
345 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG()
385 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF()
427 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG()
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| H A D | RISCVRegisterInfo.h | 46 static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) { in getLMul()
47 return static_cast<RISCVII::VLMUL>((TSFlags & VLMulShiftMask) >> VLMulShift); in getLMul()
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| H A D | RISCVInsertVSETVLI.cpp | 326 static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) { in isLMUL1OrSmaller()
533 RISCVII::VLMUL VLMul = RISCVII::LMUL_1;
611 RISCVII::VLMUL getVLMUL() const { return VLMul; } in getVLMUL()
676 void setVTYPE(RISCVII::VLMUL L, unsigned S, bool TA, bool MA) { in setVTYPE()
685 void setVLMul(RISCVII::VLMUL VLMul) { this->VLMul = VLMul; } in setVLMul()
987 RISCVII::VLMUL VLMul) { in computeVLMAX()
1027 RISCVII::VLMUL VLMul = RISCVII::getLMul(TSFlags); in computeInfoForInstr()
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| H A D | RISCVISelLowering.h | 798 static RISCVII::VLMUL getLMUL(MVT VT);
814 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
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| H A D | RISCVISelLowering.cpp | 2449 RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) { in getLMUL()
2459 return RISCVII::VLMUL::LMUL_F8; in getLMUL()
2461 return RISCVII::VLMUL::LMUL_F4; in getLMUL()
2463 return RISCVII::VLMUL::LMUL_F2; in getLMUL()
2465 return RISCVII::VLMUL::LMUL_1; in getLMUL()
2467 return RISCVII::VLMUL::LMUL_2; in getLMUL()
2469 return RISCVII::VLMUL::LMUL_4; in getLMUL()
2471 return RISCVII::VLMUL::LMUL_8; in getLMUL()
2475 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) { in getRegClassIDForLMUL()
2479 case RISCVII::VLMUL in getRegClassIDForLMUL()
8970 unsigned VLMUL = (unsigned)RISCVVType::encodeLMUL(LMulVal, Fractional); lowerGetVectorLength() local
17926 RISCVII::VLMUL VLMUL = computeKnownBitsForTargetNode() local
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| H A D | RISCVInstrInfo.cpp | 190 RISCVII::VLMUL LMul) { in isConvertibleToVMV_V_V()
220 RISCVII::VLMUL FirstLMul = RISCVVType::getVLMUL(FirstVType); in isConvertibleToVMV_V_V()
323 RISCVII::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags); in copyPhysRegVector()
342 -> std::tuple<RISCVII::VLMUL, const TargetRegisterClass &, unsigned, in copyPhysRegVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 134 static inline VLMUL getLMul(uint64_t TSFlags) { in getLMul()
135 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
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| H A D | RISCVInstPrinter.cpp | 213 if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED || in printVTypeI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2261 RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); in parseVTypeI() local
2274 RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic); in parseVTypeI()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsRISCV.td | 150 /* VLMUL */ LLVMMatchType<0>],
156 /* VLMUL */ LLVMMatchType<0>],
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 1843 RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>( in computeKnownBitsFromOperator() local
1847 uint64_t MaxVL = MaxVLEN / RISCVVType::getSEWLMULRatio(SEW, VLMUL); in computeKnownBitsFromOperator()
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