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Searched refs:VLMUL (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h73 enum VLMUL : uint8_t { enum
100 LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
105 inline static VLMUL getVLMUL(unsigned VType) { in getVLMUL()
107 return static_cast<VLMUL>(VLMul); in getVLMUL()
111 LLVM_ABI std::pair<unsigned, bool> decodeVLMUL(VLMUL VLMul);
113 inline static VLMUL encodeLMUL(unsigned LMUL, bool Fractional) { in encodeLMUL()
116 return static_cast<VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2); in encodeLMUL()
164 LLVM_ABI unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul);
166 LLVM_ABI std::optional<VLMUL> getSameRatioLMUL(unsigned SEW, VLMUL VLMUL,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp124 RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI); in createInstruments() local
127 switch (VLMUL) { in createInstruments()
183 getEEWAndEMUL(unsigned Opcode, RISCVVType::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL()
298 RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>(LMUL); in getSchedClassID() local
299 auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW); in getSchedClassID()
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp160 unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic, in encodeVTYPE()
183 std::pair<unsigned, bool> decodeVLMUL(VLMUL VLMul) { in decodeVLMUL()
224 unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul) { in getSEWLMULRatio()
236 std::optional<VLMUL> getSameRatioLMUL(unsigned SEW, VLMUL VLMul, unsigned EEW) { in getSameRatioLMUL()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h46 static inline RISCVVType::VLMUL getLMul(uint8_t TSFlags) { in getLMul()
47 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulShiftMask) >> in getLMul()
H A DRISCVISelDAGToDAG.cpp287 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG()
316 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF()
346 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG()
370 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVLXSEG()
394 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSSEG()
419 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSXSEG()
443 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVSXSEG()
483 RISCVVType::VLMUL VLMul = static_cast<RISCVVType::VLMUL>( in selectVSETVLI()
2218 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in Select()
2219 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in Select()
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H A DRISCVInsertVSETVLI.cpp271 static bool isLMUL1OrSmaller(RISCVVType::VLMUL LMUL) { in isLMUL1OrSmaller()
504 RISCVVType::VLMUL VLMul = RISCVVType::LMUL_1;
582 RISCVVType::VLMUL getVLMUL() const { return VLMul; } in getVLMUL()
647 void setVTYPE(RISCVVType::VLMUL L, unsigned S, bool TA, bool MA) { in setVTYPE()
656 void setVLMul(RISCVVType::VLMUL VLMul) { this->VLMul = VLMul; } in setVLMul()
966 RISCVVType::VLMUL VLMul) { in computeVLMAX()
1002 RISCVVType::VLMUL VLMul = RISCVII::getLMul(TSFlags); in computeInfoForInstr()
H A DRISCVExpandPseudoInsts.cpp442 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false); in expandPseudoReadVLENBViaVSETVLIX0() local
444 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true); in expandPseudoReadVLENBViaVSETVLIX0()
H A DRISCVISelLowering.h350 static RISCVVType::VLMUL getLMUL(MVT VT);
375 static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul);
H A DRISCVTargetTransformInfo.cpp920 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in isM1OrSmaller()
921 return (LMUL == RISCVVType::VLMUL::LMUL_F8 || in isM1OrSmaller()
922 LMUL == RISCVVType::VLMUL::LMUL_F4 || in isM1OrSmaller()
923 LMUL == RISCVVType::VLMUL::LMUL_F2 || in isM1OrSmaller()
924 LMUL == RISCVVType::VLMUL::LMUL_1); in isM1OrSmaller()
H A DRISCVVLOptimizer.cpp75 OperandInfo(RISCVVType::VLMUL EMUL, unsigned Log2EEW) in OperandInfo()
144 RISCVVType::VLMUL MIVLMUL = RISCVII::getLMul(MI.getDesc().TSFlags); in getEMULEqualsEEWDivSEWTimesLMUL()
H A DRISCVInstrInfo.cpp259 RISCVVType::VLMUL LMul) { in isConvertibleToVMV_V_V()
287 RISCVVType::VLMUL FirstLMul = RISCVVType::getVLMUL(FirstVType); in isConvertibleToVMV_V_V()
386 RISCVVType::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags); in copyPhysRegVector()
405 -> std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned, in copyPhysRegVector()
H A DRISCVISelLowering.cpp2515 RISCVVType::VLMUL RISCVTargetLowering::getLMUL(MVT VT) { in getLMUL()
2562 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVVType::VLMUL LMul) { in getRegClassIDForLMUL()
2581 RISCVVType::VLMUL LMUL = getLMUL(VT); in getSubregIndexByMVT()
10392 RISCVVType::VLMUL Lmul = RISCVTargetLowering::getLMUL(VT); in lowerVectorIntrinsicScalars()
10489 unsigned VLMUL = (unsigned)RISCVVType::encodeLMUL(LMulVal, Fractional); in lowerGetVectorLength() local
10494 SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT); in lowerGetVectorLength()
21057 RISCVVType::VLMUL VLMUL = in computeKnownBitsForTargetNode() local
21058 static_cast<RISCVVType::VLMUL>(Op.getConstantOperandVal(HasAVL + 2)); in computeKnownBitsForTargetNode()
21060 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMUL); in computeKnownBitsForTargetNode()
21689 lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVVType::VLMUL LMul, unsigned SEW) { in lookupMaskedIntrinsic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h150 static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) { in getLMul()
151 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
H A DRISCVInstPrinter.cpp220 if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED || in printVTypeI()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2349 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); in parseVTypeI() local
2361 RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic); in parseVTypeI()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td150 /* VLMUL */ LLVMMatchType<0>],
156 /* VLMUL */ LLVMMatchType<0>],
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp2016 RISCVVType::VLMUL VLMUL = static_cast<RISCVVType::VLMUL>( in computeKnownBitsFromOperator() local
2020 uint64_t MaxVL = MaxVLEN / RISCVVType::getSEWLMULRatio(SEW, VLMUL); in computeKnownBitsFromOperator()