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Searched refs:VLD4DUP (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td1387 (instregex "VLD4DUP(d|q)(8|16|32)$",
1388 "VLD4DUP(d|q)(8|16|32)Pseudo$")>;
1392 (instregex "VLD4DUP(d|q)(8|16|32)_UPD")>;
1394 (instregex "VLD4DUP(d|q)(8|16|32)Pseudo_UPD")>;
H A DARMISelLowering.h327 VLD4DUP, enumerator
H A DARMInstrNEON.td1615 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1616 class VLD4DUP<bits<4> op7_4, string Dt>
1626 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1627 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1628 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1635 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1636 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1637 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
H A DARMISelLowering.cpp1871 MAKE_CASE(ARMISD::VLD4DUP) in getTargetNodeName()
15941 case ARMISD::VLD4DUP: in TryCombineBaseUpdate()
16399 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
18955 case ARMISD::VLD4DUP: in PerformDAGCombine()
H A DARMISelDAGToDAG.cpp4349 case ARMISD::VLD4DUP: { in Select()