Searched refs:VLD3DUP (Results 1 – 5 of 5) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 1340 (instregex "VLD3DUP(d|q)(8|16|32)$", 1341 "VLD3DUP(d|q)(8|16|32)Pseudo$")>; 1344 (instregex "VLD3DUP(d|q)(8|16|32)_UPD")>; 1346 (instregex "VLD3DUP(d|q)(8|16|32)Pseudo_UPD")>;
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H A D | ARMISelLowering.h | 326 VLD3DUP, enumerator
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H A D | ARMInstrNEON.td | 1558 // VLD3DUP : Vector Load (single 3-element structure to all lanes) 1559 class VLD3DUP<bits<4> op7_4, string Dt> 1569 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">; 1570 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">; 1571 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">; 1578 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">; 1579 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">; 1580 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
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H A D | ARMISelLowering.cpp | 1870 MAKE_CASE(ARMISD::VLD3DUP) in getTargetNodeName() 15937 case ARMISD::VLD3DUP: in TryCombineBaseUpdate() 16396 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP() 18954 case ARMISD::VLD3DUP: in PerformDAGCombine()
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H A D | ARMISelDAGToDAG.cpp | 4341 case ARMISD::VLD3DUP: { in Select()
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