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Searched refs:VL (Results 1 – 25 of 114) sorted by relevance

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/freebsd/crypto/openssl/crypto/aes/asm/
H A Daes-riscv64-zvbb-zvkg-zvkned.pl72 my ($VL) = ("a7");
109 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "ma"]}
187 addi $VL, $VL, -4
190 @{[vslidedown_vx $V24, $V24, $VL]}
192 @{[vslidedown_vx $V16, $V16, $VL]}
246 addi $VL, $VL, -4
249 @{[vslidedown_vx $V16, $V16, $VL]}
456 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "ma"]}
460 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "ma"]}
469 slli $T0, $VL, 2
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H A Daes-riscv64-zvkb-zvkned.pl70 my ($VL) = ("t4");
107 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "mu"]}
171 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "mu"]}
177 slli $T0, $VL, 2
178 srli $CTR, $VL, 2
179 sub $LEN32, $LEN32, $VL
247 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "mu"]}
253 slli $T0, $VL, 2
254 srli $CTR, $VL, 2
255 sub $LEN32, $LEN32, $VL
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H A Daes-riscv64-zvkned.pl594 my ($VL) = ("a6");
630 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "ma"]}
631 slli $T0, $VL, 2
632 sub $LEN32, $LEN32, $VL
657 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "ma"]}
658 slli $T0, $VL, 2
659 sub $LEN32, $LEN32, $VL
684 @{[vsetvli $VL, $LEN32, "e32", "m4", "ta", "ma"]}
685 slli $T0, $VL, 2
686 sub $LEN32, $LEN32, $VL
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DVarLocBasedImpl.cpp479 VarLoc VL(MI); in CreateEntryLoc() local
480 assert(VL.Locs.size() == 1 && in CreateEntryLoc()
481 VL.Locs[0].Kind == MachineLocKind::RegisterKind); in CreateEntryLoc()
482 VL.EVKind = EntryValueLocKind::EntryValueKind; in CreateEntryLoc()
483 VL.Expr = EntryExpr; in CreateEntryLoc()
484 VL.Locs[0].Value.RegNo = Reg; in CreateEntryLoc()
485 return VL; in CreateEntryLoc()
494 VarLoc VL(MI); in CreateEntryBackupLoc() local
495 assert(VL.Locs.size() == 1 && in CreateEntryBackupLoc()
496 VL.Locs[0].Kind == MachineLocKind::RegisterKind); in CreateEntryBackupLoc()
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/freebsd/contrib/llvm-project/clang/lib/AST/
H A DDeclOpenMP.cpp31 ArrayRef<Expr *> VL) { in Create() argument
33 C, DC, {}, VL.size(), L); in Create()
34 D->setVars(VL); in Create()
45 void OMPThreadPrivateDecl::setVars(ArrayRef<Expr *> VL) { in setVars() argument
46 assert(VL.size() == Data->getNumChildren() && in setVars()
48 llvm::copy(VL, getVars().begin()); in setVars()
58 SourceLocation L, ArrayRef<Expr *> VL, in Create() argument
61 C, DC, CL, VL.size(), L); in Create()
62 D->setVars(VL); in Create()
74 void OMPAllocateDecl::setVars(ArrayRef<Expr *> VL) { in setVars() argument
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H A DOpenMPClause.cpp428 void OMPPrivateClause::setPrivateCopies(ArrayRef<Expr *> VL) { in setPrivateCopies() argument
429 assert(VL.size() == varlist_size() && in setPrivateCopies()
431 llvm::copy(VL, varlist_end()); in setPrivateCopies()
437 ArrayRef<Expr *> VL, ArrayRef<Expr *> PrivateVL) { in Create() argument
439 void *Mem = C.Allocate(totalSizeToAlloc<Expr *>(2 * VL.size())); in Create()
441 new (Mem) OMPPrivateClause(StartLoc, LParenLoc, EndLoc, VL.size()); in Create()
442 Clause->setVarRefs(VL); in Create()
453 void OMPFirstprivateClause::setPrivateCopies(ArrayRef<Expr *> VL) { in setPrivateCopies() argument
454 assert(VL.size() == varlist_size() && in setPrivateCopies()
456 llvm::copy(VL, varlist_end()); in setPrivateCopies()
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/freebsd/crypto/openssl/crypto/chacha/asm/
H A Dchacha-riscv64-v-zbb.pl85 my ( $VL ) = ( "t1" );
268 @{[vsetvli $VL, $T0, "e32", "m1", "ta", "ma"]}
269 slli $T1, $VL, 6
273 addi $T1, $VL, -1
274 @{[vsetvli $VL, $T1, "e32", "m1", "ta", "ma"]}
317 add $COUNTER0, $CURRENT_COUNTER, $VL
437 add $STATE12, $STATE12, $VL
469 slli $T0, $VL, 6
474 add $CURRENT_COUNTER, $CURRENT_COUNTER, $VL
483 @{[vsetvli $VL, $T1, "e8", "m8", "ta", "ma"]}
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp74 std::optional<unsigned> getConstant(const MachineOperand &VL) const;
151 MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc())); in tryToReduceVL() local
152 if (VL.isImm() && VL.getImm() == RISCV::VLMaxSentinel) in tryToReduceVL()
180 if (VL.isIdenticalTo(SrcVL) || !RISCV::isVLKnownLE(VL, SrcVL)) in tryToReduceVL()
183 if (!ensureDominates(VL, *Src)) in tryToReduceVL()
186 if (VL.isImm()) in tryToReduceVL()
187 SrcVL.ChangeToImmediate(VL.getImm()); in tryToReduceVL()
188 else if (VL.isReg()) in tryToReduceVL()
189 SrcVL.ChangeToRegister(VL.getReg(), false); in tryToReduceVL()
201 RISCVVectorPeephole::getConstant(const MachineOperand &VL) const { in getConstant()
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H A DRISCVInstrFormatsV.td71 let Defs = [VL, VTYPE];
87 let Defs = [VL, VTYPE];
104 let Defs = [VL, VTYPE];
123 let Uses = [VL, VTYPE];
143 let Uses = [VL, VTYPE];
162 let Uses = [VL, VTYPE];
182 let Uses = [VL, VTYPE];
201 let Uses = [VL, VTYPE];
223 let Uses = [VL, VTYPE];
245 let Uses = [VL, VTYPE];
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H A DRISCVInterleavedAccess.cpp109 Value *VL = Builder.getInt32(VTy->getNumElements()); in lowerInterleavedLoad() local
114 {BasePtr, Stride, Mask, VL}); in lowerInterleavedLoad()
121 Value *VL = ConstantInt::get(XLenTy, VTy->getNumElements()); in lowerInterleavedLoad() local
125 {LI->getPointerOperand(), Mask, VL}); in lowerInterleavedLoad()
194 Value *VL = Builder.getInt32(VTy->getNumElements()); in lowerInterleavedStore() local
199 {Data, BasePtr, Stride, Mask, VL}); in lowerInterleavedStore()
226 Value *VL = ConstantInt::get(XLenTy, VTy->getNumElements()); in lowerInterleavedStore() local
228 Ops.append({SI->getPointerOperand(), StoreMask, VL}); in lowerInterleavedStore()
259 Value *VL = ConstantInt::get(XLenTy, FVTy->getNumElements()); in lowerDeinterleaveIntrinsicToLoad() local
263 {LI->getPointerOperand(), Mask, VL}); in lowerDeinterleaveIntrinsicToLoad()
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H A DRISCVISelLowering.cpp2901 static SDValue getAllOnesMask(MVT VecVT, SDValue VL, const SDLoc &DL, in getAllOnesMask() argument
2904 return DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); in getAllOnesMask()
2911 SDValue VL = DAG.getRegister(RISCV::X0, Subtarget.getXLenVT()); in getDefaultScalableVLOps() local
2912 SDValue Mask = getAllOnesMask(VecVT, VL, DL, DAG); in getDefaultScalableVLOps()
2913 return {Mask, VL}; in getDefaultScalableVLOps()
2920 SDValue VL = DAG.getConstant(NumElts, DL, Subtarget.getXLenVT()); in getDefaultVLOps() local
2921 SDValue Mask = getAllOnesMask(ContainerVT, VL, DL, DAG); in getDefaultVLOps()
2922 return {Mask, VL}; in getDefaultVLOps()
3134 auto [Mask, VL] = getDefaultVLOps(DstVT, DstContainerVT, DL, DAG, Subtarget); in lowerFP_TO_INT_SAT()
3138 DAG.getUNDEF(Mask.getValueType()), Mask, VL}); in lowerFP_TO_INT_SAT()
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H A DRISCVCodeGenPrepare.cpp248 Value *BasePtr, *VL; in expandVPStrideLoad() local
252 m_Value(BasePtr), m_Zero(), m_AllOnes(), m_Value(VL)))) in expandVPStrideLoad()
260 if (!isKnownNonZero(VL, {*DL, DT, nullptr, &II})) in expandVPStrideLoad()
269 {Val, II.getOperand(2), VL}); in expandVPStrideLoad()
H A DRISCVInstrInfoXSfmm.td48 let Defs = [VTYPE, VL];
67 let Uses = [VTYPE, VL];
96 let Uses = [VTYPE, VL];
115 let Uses = [VTYPE, VL];
137 let Uses = [VTYPE, VL];
169 let Uses = [VTYPE, VL];
196 let Uses = [VTYPE, VL];
H A DRISCVInstrInfoXRivos.td29 let Uses = [VL, VTYPE];
50 let Uses = [VL, VTYPE];
70 // These are modeled after the int binop VL nodes
136 // have a VL operand.
142 // RI_VINSERT_VL matches the semantics of ri.vinsert.v.x. It carries a VL operand.
H A DRISCVRegisterInfo.cpp159 markSuperRegs(Reserved, RISCV::VL); in getReservedRegs()
431 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVSPILL() local
436 STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset); in lowerVSPILL()
438 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); in lowerVSPILL()
441 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVSPILL()
442 .addReg(VL) in lowerVSPILL()
469 .addReg(VL, getKillRegState(I == NF - 2)); in lowerVSPILL()
514 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in lowerVRELOAD() local
519 STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset); in lowerVRELOAD()
521 BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL); in lowerVRELOAD()
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H A DRISCVSchedSiFive7.td136 /// Cycles for reductions take approximately VL*SEW/DLEN + 5(4 + log(DLEN/SEW))
157 /// Cycles for ordered reductions take approximately 6*VL cycles
213 // The V pipeline is modeled by the VCQ, VA, VL, and VS resources. There can
233 def VL : ProcResource<1>; // Load sequencer
240 // time. The actual dequeueing into the sequencer is modeled by the VA, VL, and
259 ProcResourceKind VL, ProcResourceKind VS,
493 defm : LMULWriteResMX<"WriteVLDE", [VCQ, VL], mx, IsWorstCase>;
494 defm : LMULWriteResMX<"WriteVLDFF", [VCQ, VL], mx, IsWorstCase>;
504 defm : LMULWriteResMX<"WriteVLDM", [VCQ, VL], mx, IsWorstCase>;
521 defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [VCQ, VL],
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H A DRISCVInstrInfoZvfbf.td24 let Uses = [FRM, VL, VTYPE] in
30 RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFPException = true,
H A DRISCVISelDAGToDAG.cpp59 SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT()); in PreprocessISelDAG() local
64 Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), Src, VL); in PreprocessISelDAG()
76 SDValue VL = N->getOperand(3); in PreprocessISelDAG() local
107 VL}; in PreprocessISelDAG()
260 SDValue VL; in addVectorLoadStoreOperands() local
261 selectVLOp(Node->getOperand(CurOp++), VL); in addVectorLoadStoreOperands()
262 Operands.push_back(VL); in addVectorLoadStoreOperands()
1921 SDValue VL; in Select() local
1922 selectVLOp(Node->getOperand(3), VL); in Select()
1927 CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, MaskSEW)); in Select()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp344 static unsigned getShufflevectorNumGroups(ArrayRef<Value *> VL) { in getShufflevectorNumGroups() argument
345 if (VL.empty()) in getShufflevectorNumGroups()
347 if (!all_of(VL, IsaPred<ShuffleVectorInst>)) in getShufflevectorNumGroups()
349 auto *SV = cast<ShuffleVectorInst>(VL.front()); in getShufflevectorNumGroups()
356 if (GroupSize == 0 || (VL.size() % GroupSize) != 0) in getShufflevectorNumGroups()
359 for (size_t I = 0, E = VL.size(); I != E; I += GroupSize) { in getShufflevectorNumGroups()
360 auto *SV = cast<ShuffleVectorInst>(VL[I]); in getShufflevectorNumGroups()
362 ArrayRef<Value *> Group = VL.slice(I, GroupSize); in getShufflevectorNumGroups()
380 assert(NumGroup == (VL.size() / GroupSize) && "Unexpected number of groups"); in getShufflevectorNumGroups()
396 static SmallVector<int> calculateShufflevectorMask(ArrayRef<Value *> VL) { in calculateShufflevectorMask() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXTargetTransformInfo.h116 ArrayRef<Value *> VL = {}) const override {
123 if (Insert && !VL.empty()) {
125 return !DemandedElts[Idx] || isa<Constant>(VL[Idx]);
147 ForPoisonSrc, VL);
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dkirkwood-linkstation-lsvl.dts3 * Device Tree file for Buffalo Linkstation LS-VL
13 model = "Buffalo Linkstation LS-VL";
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp960 static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL, in buildAllOnesMask() argument
964 return MIB.buildInstr(RISCV::G_VMSET_VL, {MaskTy}, {VL}); in buildAllOnesMask()
974 auto VL = MIB.buildConstant(XLenTy, -1); in buildDefaultVLOps() local
975 auto Mask = buildAllOnesMask(VecTy, VL, MIB, MRI); in buildDefaultVLOps()
976 return {Mask, VL}; in buildDefaultVLOps()
981 Register Hi, const SrcOp &VL, MachineIRBuilder &MIB, in buildSplatPartsS64WithVL() argument
992 {Passthru, Lo, Hi, VL}); in buildSplatPartsS64WithVL()
997 const SrcOp &Scalar, const SrcOp &VL, in buildSplatSplitS64WithVL() argument
1002 Unmerge.getReg(1), VL, MIB, MRI); in buildSplatSplitS64WithVL()
1024 auto [_, VL] = buildDefaultVLOps(MRI.getType(Dst), MIB, MRI); in legalizeSplatVector()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/PBQP/
H A DReductionRules.h152 unsigned VL = V.getLength(); in hasRegisterOptions() local
155 if (VL <= 1) in hasRegisterOptions()
160 for (unsigned i = 1; i < VL; ++i) in hasRegisterOptions()
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcs43130.txt10 - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
57 VL-supply = <&dummy_vreg>;
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td194 (Address0, ..., Address{NF - 1}, Ptr, VL)
196 (Address0, ..., Address{NF - 1}, Mask, Ptr, VL)
199 Ptr, VL)
202 Ptr, VL)
210 (Address0, ..., Address{NF - 1}, Ptr, NewVL, VL)
212 (Address0, ..., Address{NF - 1}, Mask, Ptr, NewVL, VL)
215 Ptr, NewVL, VL)
218 Ptr, NewVL, VL)
223 (Address0, ..., Address{NF - 1}, Ptr, Stride, VL)
225 (Address0, ..., Address{NF - 1}, Mask, Ptr, Stride, VL)
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