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Searched refs:VGPR_32_Lo128 (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP2Instructions.td391 let DstRC = VOPDstOperand<VGPR_32_Lo128>;
392 let Ins32 = (ins VSrcFake16_f16_Lo128_Deferred:$src0, VGPR_32_Lo128:$src1, ImmOpType:$imm);
416 let DstRC = VOPDstOperand<VGPR_32_Lo128>;
417 let Ins32 = (ins VSrcFake16_f16_Lo128_Deferred:$src0, ImmOpType:$imm, VGPR_32_Lo128:$src1);
485 let DstRC = VOPDstOperand<VGPR_32_Lo128>;
917 let Src1RC32 = RegisterOperand<VGPR_32_Lo128>;
918 let Src1DPP = RegisterOperand<VGPR_32_Lo128>;
H A DSIRegisterInfo.td631 def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,
1046 (add VGPR_32_Lo128, SReg_32, LDS_DIRECT_CLASS)> {
1258 def VGPRSrc_32_Lo128 : RegisterOperand<VGPR_32_Lo128> {
H A DSIInstrInfo.td1529 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32_Lo128>,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp279 DECODE_OPERAND_REG_8(VGPR_32_Lo128) in DECODE_OPERAND_REG_8() argument