Searched refs:VGPR32 (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.h | 34 VGPR32, enumerator
52 return Value[AGPR32] ? alignTo(Value[VGPR32], 4) + Value[AGPR32] in getVGPRNum()
53 : Value[VGPR32] + Value[AGPR32]; in getVGPRNum()
55 return std::max(Value[VGPR32], Value[AGPR32]); in getVGPRNum()
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| H A D | GCNRegPressure.cpp | 47 : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
66 case VGPR32: in inc()
76 Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] += in inc()
228 OS << "VGPRs: " << RP.Value[GCNRegPressure::VGPR32] << ' ' in print()
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| H A D | AMDGPUCallingConv.td | 51 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
86 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
119 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
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| H A D | MIMGInstructions.td | 1342 // it is the only one that could have a register other than VGPR32.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 4768 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign() local
4779 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4888 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS() local
4893 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()
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