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Searched refs:VGPR0 (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp92 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
93 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
94 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
95 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
H A DAMDGPUCallingConv.td33 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
47 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
82 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
115 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
198 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
210 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
H A DGCNNSAReassign.cpp148 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
150 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs()
H A DSIInsertWaitcnts.cpp102 unsigned VGPR0; member
752 assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL); in getRegInterval()
753 Result.first = Reg - Encoding.VGPR0; in getRegInterval()
2447 Encoding.VGPR0 = in runOnMachineFunction()
2448 TRI->getEncodingValue(AMDGPU::VGPR0) & AMDGPU::HWEncoding::REG_IDX_MASK; in runOnMachineFunction()
2449 Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1; in runOnMachineFunction()
H A DGCNHazardRecognizer.cpp1796 if (!TRI.isVGPR(MRI, AmtReg) || ((AmtReg - AMDGPU::VGPR0) & 7) != 7) in fixShift64HighRegBug()
1810 static_assert(AMDGPU::VGPR0 + 1 == AMDGPU::VGPR1); in fixShift64HighRegBug()
H A DMIMGInstructions.td540 // Force vdata to VGPR0 as no result will be returned.
1196 // Force vdata to VGPR0 as no result will be returned.
1206 // Force vdata to VGPR0 as no result will be returned.
H A DSIRegisterInfo.cpp184 TmpVGPR = AMDGPU::VGPR0; in prepare()
444 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8; in isChainScratchRegister()
H A DAMDGPUCallLowering.cpp686 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
H A DSOPInstructions.td1087 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
H A DSIISelLowering.cpp2249 Register Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
2261 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2275 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2857 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4779 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4893 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()