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Searched refs:VECTOR_SPLICE (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h626 VECTOR_SPLICE, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp333 case ISD::VECTOR_SPLICE: return "vector_splice"; in getOperationName()
H A DLegalizeDAG.cpp3548 case ISD::VECTOR_SPLICE: { in ExpandNode()
5337 case ISD::VECTOR_SPLICE: { in PromoteNode()
5340 Tmp3 = DAG.getNode(ISD::VECTOR_SPLICE, dl, NVT, Tmp1, Tmp2, in PromoteNode()
H A DLegalizeIntegerTypes.cpp130 case ISD::VECTOR_SPLICE: in PromoteIntegerResult()
5706 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
H A DLegalizeVectorTypes.cpp1130 case ISD::VECTOR_SPLICE: in SplitVectorResult()
H A DSelectionDAGBuilder.cpp12510 setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, in visitVectorSplice()
H A DSelectionDAG.cpp7485 case ISD::VECTOR_SPLICE: { in getNode()
H A DTargetLowering.cpp11361 assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!"); in expandVectorSplice()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp794 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1446 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1618 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1664 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1748 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv2i1, MVT::nxv2i64); in AArch64TargetLowering()
1749 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32); in AArch64TargetLowering()
1750 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16); in AArch64TargetLowering()
1751 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8); in AArch64TargetLowering()
2121 setOperationAction(ISD::VECTOR_SPLICE, VT, Default); in addTypeForFixedLengthSVE()
7032 case ISD::VECTOR_SPLICE: in LowerOperation()
14556 SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, InVT, Vec, Vec, Idx); in LowerEXTRACT_SUBVECTOR()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td783 def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp811 ISD::VECTOR_SPLICE, VT, in RISCVTargetLowering()
897 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in RISCVTargetLowering()
1027 setOperationAction({ISD::VECTOR_REVERSE, ISD::VECTOR_SPLICE}, VT, Custom); in RISCVTargetLowering()
6836 case ISD::VECTOR_SPLICE: in LowerOperation()