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Searched refs:VECTOR_REG_CAST (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1760 MAKE_CASE(ARMISD::VECTOR_REG_CAST) in getTargetNodeName()
4255 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7946 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
7990 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
8332 Src.ShuffleVec = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
8384 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle); in ReconstructShuffle()
8667 SDValue BC = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Shuffled); in LowerVECTOR_SHUFFLE_i1()
8958 SDValue Lo = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, FromVT, V1); in LowerVECTOR_SHUFFLE()
8959 SDValue Hi = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, FromVT, in LowerVECTOR_SHUFFLE()
9190 NewV = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, NewV); in LowerCONCAT_VECTORS_i1()
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H A DARMISelLowering.h141 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register enumerator
H A DARMInstrInfo.td309 // 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a
312 // the _memory_ storage format of the vector, whereas VECTOR_REG_CAST
316 // For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of
321 // VECTOR_REG_CAST emits no code at all if the vector is already in a register.
322 def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>;
324 // In little-endian, VECTOR_REG_CAST is often turned into bitconvert during
326 // that needs to match something that's _logically_ a VECTOR_REG_CAST must
330 // matches VECTOR_REG_CAST in either endianness, and also bitconvert in the