Home
last modified time | relevance | path

Searched refs:VECTOR_REG_CAST (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1754 MAKE_CASE(ARMISD::VECTOR_REG_CAST) in getTargetNodeName()
4325 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
7998 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
8011 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
8021 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
8042 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, VDup); in LowerBUILD_VECTOR()
8383 Src.ShuffleVec = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
8436 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle); in ReconstructShuffle()
8719 SDValue BC = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Shuffled); in LowerVECTOR_SHUFFLE_i1()
9010 SDValue Lo = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, FromVT, V1); in LowerVECTOR_SHUFFLE()
[all …]
H A DARMISelLowering.h142 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register enumerator
H A DARMInstrInfo.td335 // 'VECTOR_REG_CAST' is an operation that reinterprets the contents of a
338 // the _memory_ storage format of the vector, whereas VECTOR_REG_CAST
342 // For example, 'VECTOR_REG_CAST' between v8i16 and v16i8 will map the LSB of
347 // VECTOR_REG_CAST emits no code at all if the vector is already in a register.
348 def ARMVectorRegCastImpl : SDNode<"ARMISD::VECTOR_REG_CAST", SDTUnaryOp>;
350 // In little-endian, VECTOR_REG_CAST is often turned into bitconvert during
352 // that needs to match something that's _logically_ a VECTOR_REG_CAST must
356 // matches VECTOR_REG_CAST in either endianness, and also bitconvert in the