Searched refs:VECTOR_INTERLEAVE (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 622 VECTOR_INTERLEAVE, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 347 case ISD::VECTOR_INTERLEAVE: return "vector_interleave"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 3649 case ISD::VECTOR_INTERLEAVE: { in ExpandNode()
3660 DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, {VecVT, VecVT}, in ExpandNode()
3667 SDValue L = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, HalfVTs, LOps); in ExpandNode()
3668 SDValue R = DAG.getNode(ISD::VECTOR_INTERLEAVE, dl, HalfVTs, ROps); in ExpandNode()
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| H A D | LegalizeVectorTypes.cpp | 1184 case ISD::VECTOR_INTERLEAVE: in SplitVectorResult()
3369 SDValue Res[] = {DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, in SplitVecRes_VECTOR_INTERLEAVE()
3371 DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, in SplitVecRes_VECTOR_INTERLEAVE()
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| H A D | LegalizeIntegerTypes.cpp | 136 case ISD::VECTOR_INTERLEAVE: in PromoteIntegerResult()
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| H A D | SelectionDAGBuilder.cpp | 12638 DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, DAG.getVTList(ValueVTs), InVecs); in visitVectorInterleave()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 850 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in RISCVTargetLowering()
944 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in RISCVTargetLowering()
1114 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in RISCVTargetLowering()
1161 ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE, in RISCVTargetLowering()
1269 setOperationAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE}, in RISCVTargetLowering()
1432 setOperationAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE}, in RISCVTargetLowering()
7804 case ISD::VECTOR_INTERLEAVE: in LowerOperation()
12043 SDValue NewInterleave = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, Ops); in lowerVECTOR_INTERLEAVE()
12067 SDValue Res[] = {DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, in lowerVECTOR_INTERLEAVE()
12069 DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, in lowerVECTOR_INTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1506 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
1562 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
1714 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
1765 setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom); in AArch64TargetLowering()
7508 case ISD::VECTOR_INTERLEAVE: in LowerOperation()
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