Searched refs:VECTOR_DEINTERLEAVE (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 594 VECTOR_DEINTERLEAVE, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 329 case ISD::VECTOR_DEINTERLEAVE: return "vector_deinterleave"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 1133 case ISD::VECTOR_DEINTERLEAVE: in SplitVectorResult()
3087 SDValue ResLo = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, in SplitVecRes_VECTOR_DEINTERLEAVE()
3089 SDValue ResHi = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, in SplitVecRes_VECTOR_DEINTERLEAVE()
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| H A D | LegalizeIntegerTypes.cpp | 133 case ISD::VECTOR_DEINTERLEAVE: in PromoteIntegerResult()
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| H A D | SelectionDAGBuilder.cpp | 12451 SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, in visitVectorDeinterleave()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 802 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in RISCVTargetLowering()
893 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in RISCVTargetLowering()
1024 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in RISCVTargetLowering()
6828 case ISD::VECTOR_DEINTERLEAVE: in LowerOperation()
10469 SDValue ResLo = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, in lowerVECTOR_DEINTERLEAVE()
10471 SDValue ResHi = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, in lowerVECTOR_DEINTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1424 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
1469 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
1619 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
7034 case ISD::VECTOR_DEINTERLEAVE: in LowerOperation()
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