Searched refs:VECTOR_DEINTERLEAVE (Results 1 – 8 of 8) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 611 VECTOR_DEINTERLEAVE, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 346 case ISD::VECTOR_DEINTERLEAVE: return "vector_deinterleave"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 3624 case ISD::VECTOR_DEINTERLEAVE: { in ExpandNode()
3633 SDValue L = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, HalfVTs, in ExpandNode()
3635 SDValue R = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, HalfVTs, in ExpandNode()
3642 DAG.getNode(ISD::VECTOR_DEINTERLEAVE, dl, {VecVT, VecVT}, in ExpandNode()
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| H A D | LegalizeVectorTypes.cpp | 1181 case ISD::VECTOR_DEINTERLEAVE: in SplitVectorResult()
3346 SDValue ResLo = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, in SplitVecRes_VECTOR_DEINTERLEAVE()
3348 SDValue ResHi = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, in SplitVecRes_VECTOR_DEINTERLEAVE()
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| H A D | LegalizeIntegerTypes.cpp | 137 case ISD::VECTOR_DEINTERLEAVE: in PromoteIntegerResult()
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| H A D | SelectionDAGBuilder.cpp | 12607 SDValue Res = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, in visitVectorDeinterleave()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 849 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in RISCVTargetLowering()
943 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in RISCVTargetLowering()
1113 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in RISCVTargetLowering()
1161 ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE, in RISCVTargetLowering()
1269 setOperationAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE}, in RISCVTargetLowering()
1432 setOperationAction({ISD::VECTOR_INTERLEAVE, ISD::VECTOR_DEINTERLEAVE}, in RISCVTargetLowering()
7802 case ISD::VECTOR_DEINTERLEAVE: in LowerOperation()
11854 DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, Ops); in lowerVECTOR_DEINTERLEAVE()
11875 SDValue Lo = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, in lowerVECTOR_DEINTERLEAVE()
11877 SDValue Hi = DAG.getNode(ISD::VECTOR_DEINTERLEAVE, DL, VTs, in lowerVECTOR_DEINTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1505 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
1561 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
1713 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
1764 setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom); in AArch64TargetLowering()
7506 case ISD::VECTOR_DEINTERLEAVE: in LowerOperation()
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