| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 690 VECTOR_COMPRESS, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 457 case ISD::VECTOR_COMPRESS: return "vector_compress"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 1165 case ISD::VECTOR_COMPRESS: in SplitVectorResult()
2505 if (TLI.isOperationLegal(ISD::VECTOR_COMPRESS, CheckVT) || in SplitVecRes_VECTOR_COMPRESS()
2506 TLI.isOperationCustom(ISD::VECTOR_COMPRESS, CheckVT)) { in SplitVecRes_VECTOR_COMPRESS()
2527 Lo = DAG.getNode(ISD::VECTOR_COMPRESS, DL, LoVT, Lo, LoMask, UndefPassthru); in SplitVecRes_VECTOR_COMPRESS()
2528 Hi = DAG.getNode(ISD::VECTOR_COMPRESS, DL, HiVT, Hi, HiMask, UndefPassthru); in SplitVecRes_VECTOR_COMPRESS()
3448 case ISD::VECTOR_COMPRESS: in SplitVectorOperand()
4715 case ISD::VECTOR_COMPRESS: in WidenVectorResult()
6208 return DAG.getNode(ISD::VECTOR_COMPRESS, SDLoc(N), WideVecVT, WideVec, in WidenVecRes_VECTOR_COMPRESS()
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| H A D | LegalizeVectorOps.cpp | 475 case ISD::VECTOR_COMPRESS: in LegalizeOp()
1284 case ISD::VECTOR_COMPRESS: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 93 case ISD::VECTOR_COMPRESS: in PromoteIntegerResult()
1043 return DAG.getNode(ISD::VECTOR_COMPRESS, SDLoc(N), Vec.getValueType(), Vec, in PromoteIntRes_VECTOR_COMPRESS()
2008 case ISD::VECTOR_COMPRESS: in PromoteIntegerOperand()
2580 return DAG.getNode(ISD::VECTOR_COMPRESS, SDLoc(N), VT, Vec, Mask, Passthru); in PromoteIntOp_VECTOR_COMPRESS()
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| H A D | SelectionDAGBuilder.cpp | 8268 setValue(&I, DAG.getNode(ISD::VECTOR_COMPRESS, sdl, in visitIntrinsicCall()
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| H A D | SelectionDAG.cpp | 8102 case ISD::VECTOR_COMPRESS: { in getNode()
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| H A D | DAGCombiner.cpp | 2034 case ISD::VECTOR_COMPRESS: return visitVECTOR_COMPRESS(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 894 setOperationAction(ISD::VECTOR_COMPRESS, VT, Expand); in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 981 setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom); in RISCVTargetLowering()
1133 setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom); in RISCVTargetLowering()
1163 ISD::VECTOR_COMPRESS}, in RISCVTargetLowering()
1403 setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom); in RISCVTargetLowering()
1427 ISD::VECTOR_SHUFFLE, ISD::VECTOR_COMPRESS}, in RISCVTargetLowering()
6142 return DAG.getNode(ISD::VECTOR_COMPRESS, DL, VT, V1, CompressMask, in lowerVECTOR_SHUFFLE()
8040 case ISD::VECTOR_COMPRESS: in LowerOperation()
11957 SDValue EvenWide = DAG.getNode(ISD::VECTOR_COMPRESS, DL, ConcatVT, Concat, in lowerVECTOR_DEINTERLEAVE()
11959 SDValue OddWide = DAG.getNode(ISD::VECTOR_COMPRESS, DL, ConcatVT, Concat, in lowerVECTOR_DEINTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 815 def vector_compress : SDNode<"ISD::VECTOR_COMPRESS", SDTVectorCompress>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2168 setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom); in X86TargetLowering()
2173 setOperationAction(ISD::VECTOR_COMPRESS, VT, Legal); in X86TargetLowering()
2179 setOperationAction(ISD::VECTOR_COMPRESS, VT, Legal); in X86TargetLowering()
2184 setOperationAction(ISD::VECTOR_COMPRESS, VT, Legal); in X86TargetLowering()
2189 setOperationAction(ISD::VECTOR_COMPRESS, VT, Legal); in X86TargetLowering()
18415 DAG.getNode(ISD::VECTOR_COMPRESS, DL, LargeVecVT, Vec, Mask, Passthru); in lowerVECTOR_COMPRESS()
18431 DAG.getNode(ISD::VECTOR_COMPRESS, DL, LargeVecVT, Vec, Mask, Passthru); in lowerVECTOR_COMPRESS()
33592 case ISD::VECTOR_COMPRESS: return lowerVECTOR_COMPRESS(Op, Subtarget, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1936 setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom); in AArch64TargetLowering()
1942 setOperationAction(ISD::VECTOR_COMPRESS, VT, Custom); in AArch64TargetLowering()
7440 case ISD::VECTOR_COMPRESS: in LowerOperation()
27707 case ISD::VECTOR_COMPRESS: in ReplaceNodeResults()
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