| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1413 VECREDUCE_UMIN, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 541 case ISD::VECREDUCE_UMIN: return "vecreduce_umin"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 488 case ISD::VECREDUCE_UMIN: in LegalizeOp()
1100 case ISD::VECREDUCE_UMIN: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 290 case ISD::VECREDUCE_UMIN: in PromoteIntegerResult()
2008 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break; in PromoteIntegerOperand()
2581 case ISD::VECREDUCE_UMIN: in getExtendForIntVecReduction()
2641 TLI.isOperationLegalOrCustom(ISD::VECREDUCE_UMIN, InVT)) { in PromoteIntOp_VECREDUCE()
2642 Opcode = ISD::VECREDUCE_UMIN; in PromoteIntOp_VECREDUCE()
2932 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break; in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 804 case ISD::VECREDUCE_UMIN: in ScalarizeVectorOperand()
3233 case ISD::VECREDUCE_UMIN: in SplitVectorOperand()
6444 case ISD::VECREDUCE_UMIN: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1208 case ISD::VECREDUCE_UMIN: in LegalizeOp()
4314 case ISD::VECREDUCE_UMIN: in ExpandNode()
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| H A D | SelectionDAG.cpp | 463 case ISD::VECREDUCE_UMIN: in getVecReduceBaseOpcode()
6208 case ISD::VECREDUCE_UMIN: in getNode()
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| H A D | DAGCombiner.cpp | 1985 case ISD::VECREDUCE_UMIN: in visit()
5740 return ISD::VECREDUCE_UMIN; in visitIMINMAX()
26733 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; in visitVECREDUCE()
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| H A D | SelectionDAGBuilder.cpp | 10757 Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1); in visitVectorReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 788 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 309 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal); in addMVEVectorTypes()
1027 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in ARMTargetLowering()
10377 case ISD::VECREDUCE_UMIN: in LowerVecReduceMinMax()
10423 case ISD::VECREDUCE_UMIN: in LowerVecReduceMinMax()
10670 case ISD::VECREDUCE_UMIN: in LowerOperation()
13241 if ((TrueVal->getOpcode() == ISD::VECREDUCE_UMIN || in PerformSELECTCombine()
13242 FalseVal->getOpcode() == ISD::VECREDUCE_UMIN) && in PerformSELECTCombine()
13270 case ISD::VECREDUCE_UMIN: in PerformSELECTCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1309 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in AArch64TargetLowering()
1465 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); in AArch64TargetLowering()
1729 setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
2118 setOperationAction(ISD::VECREDUCE_UMIN, VT, Default); in addTypeForFixedLengthSVE()
6959 case ISD::VECREDUCE_UMIN: in LowerOperation()
15219 Result = DAG.getNode(ISD::VECREDUCE_UMIN, DL, ExtendedVT, Extended); in getVectorBitwiseReduce()
15301 case ISD::VECREDUCE_UMIN: in LowerVECREDUCE()
15336 case ISD::VECREDUCE_UMIN: in LowerVECREDUCE()
26194 case ISD::VECREDUCE_UMIN: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 352 ISD::VECREDUCE_SMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_UMAX}; in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 494 def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 724 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN}; in RISCVTargetLowering()
1262 ISD::VECREDUCE_UMIN}, in RISCVTargetLowering()
6778 case ISD::VECREDUCE_UMIN: in LowerOperation()
9683 case ISD::VECREDUCE_UMIN: in getRVVReductionOp()
12887 case ISD::VECREDUCE_UMIN: in ReplaceNodeResults()
12925 return ISD::VECREDUCE_UMIN; in getVecReduceOpcode()
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