/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 1412 VECREDUCE_UMAX, enumerator
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 540 case ISD::VECREDUCE_UMAX: return "vecreduce_umax"; in getOperationName()
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H A D | LegalizeVectorOps.cpp | 487 case ISD::VECREDUCE_UMAX: in LegalizeOp() 1099 case ISD::VECREDUCE_UMAX: in Expand()
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H A D | LegalizeIntegerTypes.cpp | 289 case ISD::VECREDUCE_UMAX: in PromoteIntegerResult() 2007 case ISD::VECREDUCE_UMAX: in PromoteIntegerOperand() 2580 case ISD::VECREDUCE_UMAX: in getExtendForIntVecReduction() 2622 TLI.isOperationLegalOrCustom(ISD::VECREDUCE_UMAX, InVT)) { in PromoteIntOp_VECREDUCE() 2623 Opcode = ISD::VECREDUCE_UMAX; in PromoteIntOp_VECREDUCE() 2931 case ISD::VECREDUCE_UMAX: in ExpandIntegerResult()
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H A D | LegalizeVectorTypes.cpp | 803 case ISD::VECREDUCE_UMAX: in ScalarizeVectorOperand() 3232 case ISD::VECREDUCE_UMAX: in SplitVectorOperand() 6443 case ISD::VECREDUCE_UMAX: in WidenVectorOperand()
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H A D | LegalizeDAG.cpp | 1207 case ISD::VECREDUCE_UMAX: in LegalizeOp() 4313 case ISD::VECREDUCE_UMAX: in ExpandNode()
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H A D | SelectionDAGBuilder.cpp | 8062 SDValue Max = DAG.getNode(ISD::VECREDUCE_UMAX, DL, NewEltTy, And); in visitIntrinsicCall() 10754 Res = DAG.getNode(ISD::VECREDUCE_UMAX, dl, VT, Op1); in visitVectorReduce()
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H A D | SelectionDAG.cpp | 460 case ISD::VECREDUCE_UMAX: in getVecReduceBaseOpcode() 6203 case ISD::VECREDUCE_UMAX: in getNode()
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H A D | DAGCombiner.cpp | 1984 case ISD::VECREDUCE_UMAX: in visit() 5742 return ISD::VECREDUCE_UMAX; in visitIMINMAX() 26733 ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX; in visitVECREDUCE()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 788 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 307 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal); in addMVEVectorTypes() 1025 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in ARMTargetLowering() 10380 case ISD::VECREDUCE_UMAX: in LowerVecReduceMinMax() 10424 case ISD::VECREDUCE_UMAX: in LowerVecReduceMinMax() 10671 case ISD::VECREDUCE_UMAX: in LowerOperation() 13253 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_UMAX || in PerformSELECTCombine() 13254 FalseVal->getOpcode() == ISD::VECREDUCE_UMAX) && in PerformSELECTCombine() 13272 case ISD::VECREDUCE_UMAX: in PerformSELECTCombine()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1308 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in AArch64TargetLowering() 1466 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); in AArch64TargetLowering() 1728 setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom); in AArch64TargetLowering() 2117 setOperationAction(ISD::VECREDUCE_UMAX, VT, Default); in addTypeForFixedLengthSVE() 6958 case ISD::VECREDUCE_UMAX: in LowerOperation() 15222 Result = DAG.getNode(ISD::VECREDUCE_UMAX, DL, ExtendedVT, Extended); in getVectorBitwiseReduce() 15299 case ISD::VECREDUCE_UMAX: in LowerVECREDUCE() 15334 case ISD::VECREDUCE_UMAX: in LowerVECREDUCE() 26193 case ISD::VECREDUCE_UMAX: in ReplaceNodeResults()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 352 ISD::VECREDUCE_SMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_UMAX}; in initVPUActions()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 492 def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 724 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN}; in RISCVTargetLowering() 1261 ISD::VECREDUCE_SMIN, ISD::VECREDUCE_UMAX, in RISCVTargetLowering() 6776 case ISD::VECREDUCE_UMAX: in LowerOperation() 9677 case ISD::VECREDUCE_UMAX: in getRVVReductionOp() 12885 case ISD::VECREDUCE_UMAX: in ReplaceNodeResults() 12921 return ISD::VECREDUCE_UMAX; in getVecReduceOpcode()
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