Searched refs:VECREDUCE_SMIN (Results 1 – 15 of 15) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1411 VECREDUCE_SMIN, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 539 case ISD::VECREDUCE_SMIN: return "vecreduce_smin"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 486 case ISD::VECREDUCE_SMIN: in LegalizeOp()
1098 case ISD::VECREDUCE_SMIN: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 288 case ISD::VECREDUCE_SMIN: in PromoteIntegerResult()
2006 case ISD::VECREDUCE_SMIN: in PromoteIntegerOperand()
2576 case ISD::VECREDUCE_SMIN: in getExtendForIntVecReduction()
2930 case ISD::VECREDUCE_SMIN: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 802 case ISD::VECREDUCE_SMIN: in ScalarizeVectorOperand()
3231 case ISD::VECREDUCE_SMIN: in SplitVectorOperand()
6442 case ISD::VECREDUCE_SMIN: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1206 case ISD::VECREDUCE_SMIN: in LegalizeOp()
4312 case ISD::VECREDUCE_SMIN: in ExpandNode()
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| H A D | SelectionDAG.cpp | 457 case ISD::VECREDUCE_SMIN: in getVecReduceBaseOpcode()
6202 case ISD::VECREDUCE_SMIN: in getNode()
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| H A D | SelectionDAGBuilder.cpp | 10751 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); in visitVectorReduce()
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| H A D | DAGCombiner.cpp | 1983 case ISD::VECREDUCE_SMIN: in visit()
5736 return ISD::VECREDUCE_SMIN; in visitIMINMAX()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 787 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 308 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal); in addMVEVectorTypes()
1026 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in ARMTargetLowering()
10383 case ISD::VECREDUCE_SMIN: in LowerVecReduceMinMax()
10427 case ISD::VECREDUCE_SMIN: in LowerVecReduceMinMax()
10672 case ISD::VECREDUCE_SMIN: in LowerOperation()
13247 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMIN || in PerformSELECTCombine()
13248 FalseVal->getOpcode() == ISD::VECREDUCE_SMIN) && in PerformSELECTCombine()
13271 case ISD::VECREDUCE_SMIN: in PerformSELECTCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1307 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
1467 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
1727 setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
2116 setOperationAction(ISD::VECREDUCE_SMIN, VT, Default); in addTypeForFixedLengthSVE()
6957 case ISD::VECREDUCE_SMIN: in LowerOperation()
15297 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
15332 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
26192 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 493 def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 723 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in RISCVTargetLowering()
1261 ISD::VECREDUCE_SMIN, ISD::VECREDUCE_UMAX, in RISCVTargetLowering()
6779 case ISD::VECREDUCE_SMIN: in LowerOperation()
9686 case ISD::VECREDUCE_SMIN: in getRVVReductionOp()
12886 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
12927 return ISD::VECREDUCE_SMIN; in getVecReduceOpcode()
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