Searched refs:VECREDUCE_SMAX (Results 1 – 15 of 15) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1410 VECREDUCE_SMAX, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 538 case ISD::VECREDUCE_SMAX: return "vecreduce_smax"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 485 case ISD::VECREDUCE_SMAX: in LegalizeOp()
1097 case ISD::VECREDUCE_SMAX: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 287 case ISD::VECREDUCE_SMAX: in PromoteIntegerResult()
2005 case ISD::VECREDUCE_SMAX: in PromoteIntegerOperand()
2575 case ISD::VECREDUCE_SMAX: in getExtendForIntVecReduction()
2929 case ISD::VECREDUCE_SMAX: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 801 case ISD::VECREDUCE_SMAX: in ScalarizeVectorOperand()
3230 case ISD::VECREDUCE_SMAX: in SplitVectorOperand()
6441 case ISD::VECREDUCE_SMAX: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1205 case ISD::VECREDUCE_SMAX: in LegalizeOp()
4311 case ISD::VECREDUCE_SMAX: in ExpandNode()
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| H A D | SelectionDAG.cpp | 454 case ISD::VECREDUCE_SMAX: in getVecReduceBaseOpcode()
6207 case ISD::VECREDUCE_SMAX: in getNode()
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| H A D | SelectionDAGBuilder.cpp | 10748 Res = DAG.getNode(ISD::VECREDUCE_SMAX, dl, VT, Op1); in visitVectorReduce()
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| H A D | DAGCombiner.cpp | 1982 case ISD::VECREDUCE_SMAX: in visit()
5738 return ISD::VECREDUCE_SMAX; in visitIMINMAX()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 787 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 306 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal); in addMVEVectorTypes()
1024 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in ARMTargetLowering()
10386 case ISD::VECREDUCE_SMAX: in LowerVecReduceMinMax()
10428 case ISD::VECREDUCE_SMAX: in LowerVecReduceMinMax()
10673 case ISD::VECREDUCE_SMAX: in LowerOperation()
13259 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMAX || in PerformSELECTCombine()
13260 FalseVal->getOpcode() == ISD::VECREDUCE_SMAX) && in PerformSELECTCombine()
13273 case ISD::VECREDUCE_SMAX: in PerformSELECTCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 352 ISD::VECREDUCE_SMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_UMAX}; in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1306 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
1468 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); in AArch64TargetLowering()
1726 setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
2115 setOperationAction(ISD::VECREDUCE_SMAX, VT, Default); in addTypeForFixedLengthSVE()
6956 case ISD::VECREDUCE_SMAX: in LowerOperation()
15295 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
15330 case ISD::VECREDUCE_SMAX: in LowerVECREDUCE()
26191 case ISD::VECREDUCE_SMAX: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 491 def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 723 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in RISCVTargetLowering()
1260 setOperationAction({ISD::VECREDUCE_ADD, ISD::VECREDUCE_SMAX, in RISCVTargetLowering()
6777 case ISD::VECREDUCE_SMAX: in LowerOperation()
9680 case ISD::VECREDUCE_SMAX: in getRVVReductionOp()
12884 case ISD::VECREDUCE_SMAX: in ReplaceNodeResults()
12923 return ISD::VECREDUCE_SMAX; in getVecReduceOpcode()
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