| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1408 VECREDUCE_OR, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 536 case ISD::VECREDUCE_OR: return "vecreduce_or"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 483 case ISD::VECREDUCE_OR: in LegalizeOp()
1095 case ISD::VECREDUCE_OR: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 285 case ISD::VECREDUCE_OR: in PromoteIntegerResult()
2003 case ISD::VECREDUCE_OR: in PromoteIntegerOperand()
2567 case ISD::VECREDUCE_OR: in getExtendForIntVecReduction()
2620 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2621 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_OR, InVT) && in PromoteIntOp_VECREDUCE()
2927 case ISD::VECREDUCE_OR: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 799 case ISD::VECREDUCE_OR: in ScalarizeVectorOperand()
3228 case ISD::VECREDUCE_OR: in SplitVectorOperand()
6439 case ISD::VECREDUCE_OR: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1203 case ISD::VECREDUCE_OR: in LegalizeOp()
4309 case ISD::VECREDUCE_OR: in ExpandNode()
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| H A D | SelectionDAG.cpp | 448 case ISD::VECREDUCE_OR: in getVecReduceBaseOpcode()
6205 return getNode(ISD::VECREDUCE_OR, DL, VT, N1); in getNode()
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| H A D | DAGCombiner.cpp | 1980 case ISD::VECREDUCE_OR: in visit()
7963 reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, DL, VT, N0, N1)) in visitOR()
26731 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
26746 if ((Opcode == ISD::VECREDUCE_OR && in visitVECREDUCE()
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| H A D | SelectionDAGBuilder.cpp | 10742 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); in visitVectorReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 786 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1126 setTargetDAGCombine(ISD::VECREDUCE_OR); in AArch64TargetLowering()
1311 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1316 setOperationAction(ISD::VECREDUCE_OR, MVT::v2i64, Custom); in AArch64TargetLowering()
1463 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1524 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1737 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
2113 setOperationAction(ISD::VECREDUCE_OR, VT, Default); in addTypeForFixedLengthSVE()
6954 case ISD::VECREDUCE_OR: in LowerOperation()
15175 case ISD::VECREDUCE_OR: in getVectorBitwiseReduce()
15276 Op.getOpcode() == ISD::VECREDUCE_OR || in LowerVECREDUCE()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 722 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
771 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1176 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
6782 case ISD::VECREDUCE_OR: in LowerOperation()
9692 case ISD::VECREDUCE_OR: in getRVVReductionOp()
9718 Op.getOpcode() == ISD::VECREDUCE_OR || in lowerVectorMaskVecReduction()
9759 case ISD::VECREDUCE_OR: in lowerVectorMaskVecReduction()
12882 case ISD::VECREDUCE_OR: in ReplaceNodeResults()
12931 return ISD::VECREDUCE_OR; in getVecReduceOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 312 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addMVEVectorTypes()
10303 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break; in LowerVecReduce()
10662 case ISD::VECREDUCE_OR: in LowerOperation()
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