| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1488 VECREDUCE_OR, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 558 case ISD::VECREDUCE_OR: return "vecreduce_or"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 502 case ISD::VECREDUCE_OR: in LegalizeOp()
1226 case ISD::VECREDUCE_OR: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 305 case ISD::VECREDUCE_OR: in PromoteIntegerResult()
2054 case ISD::VECREDUCE_OR: in PromoteIntegerOperand()
2703 case ISD::VECREDUCE_OR: in getExtendForIntVecReduction()
2756 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2757 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_OR, InVT) && in PromoteIntOp_VECREDUCE()
3110 case ISD::VECREDUCE_OR: in ExpandIntegerResult()
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| H A D | LegalizeVectorTypes.cpp | 812 case ISD::VECREDUCE_OR: in ScalarizeVectorOperand()
3508 case ISD::VECREDUCE_OR: in SplitVectorOperand()
6886 case ISD::VECREDUCE_OR: in WidenVectorOperand()
7652 case ISD::VECREDUCE_OR: in getExtendForIntVecReduction()
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| H A D | LegalizeDAG.cpp | 1233 case ISD::VECREDUCE_OR: in LegalizeOp()
4447 case ISD::VECREDUCE_OR: in ExpandNode()
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| H A D | DAGCombiner.cpp | 2049 case ISD::VECREDUCE_OR: in visit()
8423 reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, DL, VT, N0, N1)) in visitOR()
27832 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
27847 if ((Opcode == ISD::VECREDUCE_OR && in visitVECREDUCE()
27856 if ((Opcode == ISD::VECREDUCE_OR || Opcode == ISD::VECREDUCE_AND || in visitVECREDUCE()
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| H A D | SelectionDAGBuilder.cpp | 6490 SDValue AnyActive = DAG.getNode(ISD::VECREDUCE_OR, sdl, BoolVT, Mask); in visitVectorExtractLastActive()
10904 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); in visitVectorReduce()
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| H A D | SelectionDAG.cpp | 460 case ISD::VECREDUCE_OR: in getVecReduceBaseOpcode()
6619 return getNode(ISD::VECREDUCE_OR, DL, VT, N1); in getNode()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 635 vector_reduce_or, VECREDUCE_OR)
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 883 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1171 setTargetDAGCombine(ISD::VECREDUCE_OR); in AArch64TargetLowering()
1366 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1371 setOperationAction(ISD::VECREDUCE_OR, MVT::v2i64, Custom); in AArch64TargetLowering()
1555 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1615 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1866 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
2350 setOperationAction(ISD::VECREDUCE_OR, VT, Default); in addTypeForFixedLengthSVE()
7422 case ISD::VECREDUCE_OR: in LowerOperation()
15948 case ISD::VECREDUCE_OR: in getVectorBitwiseReduce()
16074 Op.getOpcode() == ISD::VECREDUCE_OR || in LowerVECREDUCE()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 765 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
818 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
1290 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
7758 case ISD::VECREDUCE_OR: in LowerOperation()
11084 case ISD::VECREDUCE_OR: in getRVVReductionOp()
11110 Op.getOpcode() == ISD::VECREDUCE_OR || in lowerVectorMaskVecReduction()
11150 case ISD::VECREDUCE_OR: in lowerVectorMaskVecReduction()
14771 case ISD::VECREDUCE_OR: in ReplaceNodeResults()
14820 return ISD::VECREDUCE_OR; in getVecReduceOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 349 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 317 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addMVEVectorTypes()
10352 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break; in LowerVecReduce()
10723 case ISD::VECREDUCE_OR: in LowerOperation()
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