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Searched refs:VECREDUCE_FMUL (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1394 VECREDUCE_FMUL, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp531 case ISD::VECREDUCE_FMUL: return "vecreduce_fmul"; in getOperationName()
H A DLegalizeVectorOps.cpp490 case ISD::VECREDUCE_FMUL: in LegalizeOp()
1102 case ISD::VECREDUCE_FMUL: in Expand()
H A DLegalizeFloatTypes.cpp163 case ISD::VECREDUCE_FMUL: in SoftenFloatResult()
2662 case ISD::VECREDUCE_FMUL: in PromoteFloatResult()
3098 case ISD::VECREDUCE_FMUL: in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp795 case ISD::VECREDUCE_FMUL: in ScalarizeVectorOperand()
3224 case ISD::VECREDUCE_FMUL: in SplitVectorOperand()
6435 case ISD::VECREDUCE_FMUL: in WidenVectorOperand()
H A DLegalizeDAG.cpp1199 case ISD::VECREDUCE_FMUL: in LegalizeOp()
4305 case ISD::VECREDUCE_FMUL: in ExpandNode()
H A DSelectionDAGBuilder.cpp10727 DAG.getNode(ISD::VECREDUCE_FMUL, dl, VT, Op2, SDFlags), in visitVectorReduce()
H A DSelectionDAG.cpp434 case ISD::VECREDUCE_FMUL: in getVecReduceBaseOpcode()
H A DDAGCombiner.cpp1976 case ISD::VECREDUCE_FMUL: in visit()
16998 if (SDValue SD = reassociateReduction(ISD::VECREDUCE_FMUL, ISD::FMUL, DL, in visitFMUL()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp785 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp369 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom); in addMVEVectorTypes()
394 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom); in addMVEVectorTypes()
398 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom); in addMVEVectorTypes()
10300 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break; in LowerVecReduce()
10666 case ISD::VECREDUCE_FMUL: in LowerOperation()