Searched refs:VECREDUCE_FMINIMUM (Results 1 – 13 of 13) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1401 VECREDUCE_FMINIMUM, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 545 case ISD::VECREDUCE_FMINIMUM: return "vecreduce_fminimum"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 494 case ISD::VECREDUCE_FMINIMUM: in LegalizeOp()
1106 case ISD::VECREDUCE_FMINIMUM: in Expand()
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| H A D | LegalizeFloatTypes.cpp | 167 case ISD::VECREDUCE_FMINIMUM: R = SoftenFloatRes_VECREDUCE(N); break; in SoftenFloatResult()
2666 case ISD::VECREDUCE_FMINIMUM: in PromoteFloatResult()
3102 case ISD::VECREDUCE_FMINIMUM: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorTypes.cpp | 808 case ISD::VECREDUCE_FMINIMUM: in ScalarizeVectorOperand()
3237 case ISD::VECREDUCE_FMINIMUM: in SplitVectorOperand()
6448 case ISD::VECREDUCE_FMINIMUM: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1212 case ISD::VECREDUCE_FMINIMUM: in LegalizeOp()
4318 case ISD::VECREDUCE_FMINIMUM: in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 10769 Res = DAG.getNode(ISD::VECREDUCE_FMINIMUM, dl, VT, Op1, SDFlags); in visitVectorReduce()
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| H A D | SelectionDAG.cpp | 475 case ISD::VECREDUCE_FMINIMUM: in getVecReduceBaseOpcode()
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| H A D | DAGCombiner.cpp | 1989 case ISD::VECREDUCE_FMINIMUM: return visitVECREDUCE(N); in visit()
18155 ? (IsMin ? ISD::VECREDUCE_FMINIMUM : ISD::VECREDUCE_FMAXIMUM) in visitFMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 789 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 498 def vecreduce_fminimum : SDNode<"ISD::VECREDUCE_FMINIMUM", SDTFPVecReduce>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 728 ISD::VECREDUCE_FMAX, ISD::VECREDUCE_FMINIMUM, ISD::VECREDUCE_FMAXIMUM}; in RISCVTargetLowering()
6792 case ISD::VECREDUCE_FMINIMUM: in LowerOperation()
9902 case ISD::VECREDUCE_FMINIMUM: in getRVVFPReductionOpAndOperands()
9910 (Opcode == ISD::VECREDUCE_FMIN || Opcode == ISD::VECREDUCE_FMINIMUM) in getRVVFPReductionOpAndOperands()
9939 if (Op.getOpcode() != ISD::VECREDUCE_FMINIMUM && in lowerFPVECREDUCE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1298 setOperationAction(ISD::VECREDUCE_FMINIMUM, VT, Legal); in AArch64TargetLowering()
1617 setOperationAction(ISD::VECREDUCE_FMINIMUM, VT, Custom); in AArch64TargetLowering()
2112 setOperationAction(ISD::VECREDUCE_FMINIMUM, VT, Default); in addTypeForFixedLengthSVE()
6964 case ISD::VECREDUCE_FMINIMUM: in LowerOperation()
15313 case ISD::VECREDUCE_FMINIMUM: in LowerVECREDUCE()
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