Searched refs:VECREDUCE_FMIN (Results 1 – 14 of 14) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1397 VECREDUCE_FMIN, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 543 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 492 case ISD::VECREDUCE_FMIN: in LegalizeOp()
1104 case ISD::VECREDUCE_FMIN: in Expand()
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| H A D | LegalizeFloatTypes.cpp | 164 case ISD::VECREDUCE_FMIN: in SoftenFloatResult()
2663 case ISD::VECREDUCE_FMIN: in PromoteFloatResult()
3099 case ISD::VECREDUCE_FMIN: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorTypes.cpp | 806 case ISD::VECREDUCE_FMIN: in ScalarizeVectorOperand()
3235 case ISD::VECREDUCE_FMIN: in SplitVectorOperand()
6446 case ISD::VECREDUCE_FMIN: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1210 case ISD::VECREDUCE_FMIN: in LegalizeOp()
4316 case ISD::VECREDUCE_FMIN: in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 10763 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags); in visitVectorReduce()
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| H A D | SelectionDAG.cpp | 469 case ISD::VECREDUCE_FMIN: in getVecReduceBaseOpcode()
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| H A D | DAGCombiner.cpp | 1987 case ISD::VECREDUCE_FMIN: in visit()
18156 : (IsMin ? ISD::VECREDUCE_FMIN : ISD::VECREDUCE_FMAX), in visitFMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 789 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 496 def vecreduce_fmin : SDNode<"ISD::VECREDUCE_FMIN", SDTFPVecReduce>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 370 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in addMVEVectorTypes()
395 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom); in addMVEVectorTypes()
399 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom); in addMVEVectorTypes()
10306 case ISD::VECREDUCE_FMIN: BaseOpcode = ISD::FMINNUM; break; in LowerVecReduce()
10667 case ISD::VECREDUCE_FMIN: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1296 setOperationAction(ISD::VECREDUCE_FMIN, VT, Legal); in AArch64TargetLowering()
1615 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in AArch64TargetLowering()
2110 setOperationAction(ISD::VECREDUCE_FMIN, VT, Default); in addTypeForFixedLengthSVE()
6962 case ISD::VECREDUCE_FMIN: in LowerOperation()
15309 case ISD::VECREDUCE_FMIN: in LowerVECREDUCE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 727 ISD::VECREDUCE_FADD, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_FMIN, in RISCVTargetLowering()
6789 case ISD::VECREDUCE_FMIN: in LowerOperation()
9904 case ISD::VECREDUCE_FMIN: in getRVVFPReductionOpAndOperands()
9910 (Opcode == ISD::VECREDUCE_FMIN || Opcode == ISD::VECREDUCE_FMINIMUM) in getRVVFPReductionOpAndOperands()
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