Searched refs:VECREDUCE_FMAX (Results 1 – 14 of 14) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1396 VECREDUCE_FMAX, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 542 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 491 case ISD::VECREDUCE_FMAX: in LegalizeOp()
1103 case ISD::VECREDUCE_FMAX: in Expand()
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| H A D | LegalizeFloatTypes.cpp | 165 case ISD::VECREDUCE_FMAX: in SoftenFloatResult()
2664 case ISD::VECREDUCE_FMAX: in PromoteFloatResult()
3100 case ISD::VECREDUCE_FMAX: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorTypes.cpp | 805 case ISD::VECREDUCE_FMAX: in ScalarizeVectorOperand()
3234 case ISD::VECREDUCE_FMAX: in SplitVectorOperand()
6445 case ISD::VECREDUCE_FMAX: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 1209 case ISD::VECREDUCE_FMAX: in LegalizeOp()
4315 case ISD::VECREDUCE_FMAX: in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 10760 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); in visitVectorReduce()
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| H A D | SelectionDAG.cpp | 466 case ISD::VECREDUCE_FMAX: in getVecReduceBaseOpcode()
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| H A D | DAGCombiner.cpp | 1986 case ISD::VECREDUCE_FMAX: in visit()
18156 : (IsMin ? ISD::VECREDUCE_FMIN : ISD::VECREDUCE_FMAX), in visitFMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 788 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 497 def vecreduce_fmax : SDNode<"ISD::VECREDUCE_FMAX", SDTFPVecReduce>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 371 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addMVEVectorTypes()
396 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom); in addMVEVectorTypes()
400 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom); in addMVEVectorTypes()
10305 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
10668 case ISD::VECREDUCE_FMAX: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1295 setOperationAction(ISD::VECREDUCE_FMAX, VT, Legal); in AArch64TargetLowering()
1614 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
2109 setOperationAction(ISD::VECREDUCE_FMAX, VT, Default); in addTypeForFixedLengthSVE()
6961 case ISD::VECREDUCE_FMAX: in LowerOperation()
15307 case ISD::VECREDUCE_FMAX: in LowerVECREDUCE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 728 ISD::VECREDUCE_FMAX, ISD::VECREDUCE_FMINIMUM, ISD::VECREDUCE_FMAXIMUM}; in RISCVTargetLowering()
6790 case ISD::VECREDUCE_FMAX: in LowerOperation()
9905 case ISD::VECREDUCE_FMAX: { in getRVVFPReductionOpAndOperands()
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