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Searched refs:VCMP (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp277 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks() local
278 LLVM_DEBUG(dbgs() << " folding VCMP into VPST: "; VCMP->dump()); in InsertVPTBlocks()
281 MIBuilder.add(VCMP->getOperand(1)); in InsertVPTBlocks()
282 MIBuilder.add(VCMP->getOperand(2)); in InsertVPTBlocks()
283 MIBuilder.add(VCMP->getOperand(3)); in InsertVPTBlocks()
288 make_range(VCMP->getIterator(), MI->getIterator())) { in InsertVPTBlocks()
289 MII.clearRegisterKills(VCMP->getOperand(1).getReg(), TRI); in InsertVPTBlocks()
290 MII.clearRegisterKills(VCMP->getOperand(2).getReg(), TRI); in InsertVPTBlocks()
293 VCMP->eraseFromParent(); in InsertVPTBlocks()
H A DARMLowOverheadLoops.cpp1634 MachineInstr *VCMP = in ConvertVPTBlocks() local
1641 if (!VCMP) { in ConvertVPTBlocks()
1653 ReplaceVCMPWithVPT(VCMP, VCMP); in ConvertVPTBlocks()
1681 MachineInstr *VCMP = VprDef; in ConvertVPTBlocks() local
1687 if (std::none_of(++MachineBasicBlock::iterator(VCMP), in ConvertVPTBlocks()
1689 RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) && in ConvertVPTBlocks()
1690 RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) { in ConvertVPTBlocks()
1691 ReplaceVCMPWithVPT(VCMP, VPST); in ConvertVPTBlocks()
H A DARMScheduleM4.td130 def : M4UnitL1I<(instregex "VMOVS", "FCONSTS", "VCMP", "VNEG", "VABS")>;
H A DARMISelLowering.h147 VCMP, // Vector compare. enumerator
H A DARMScheduleM7.td425 // VCMP
H A DARMScheduleR52.td794 (instregex "(VCEQ|VCGE|VCGT|VCLE|VCLT|VCLZ|VCMP|VCMPE|VCNT)")>;
H A DARMScheduleSwift.td605 (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>;
H A DARMISelLowering.cpp1764 MAKE_CASE(ARMISD::VCMP) in getTargetNodeName()
6861 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0, in LowerVSETCC()
6863 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1, in LowerVSETCC()
6873 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0, in LowerVSETCC()
6875 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1, in LowerVSETCC()
6949 Result = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1, in LowerVSETCC()
14666 if (N->getOpcode() == ARMISD::VCMP) in getVCMPCondCode()
14689 if (V->getOpcode() == ARMISD::VCMP || V->getOpcode() == ARMISD::VCMPZ) in PerformORCombine_i1()
14829 (N0->getOpcode() == ARMISD::VCMP || N0->getOpcode() == ARMISD::VCMPZ)) { in PerformXORCombine()
14836 if (N0->getOpcode() == ARMISD::VCMP) in PerformXORCombine()
[all …]
H A DARMScheduleA57.td729 (instregex "VCMP(D|S|H|ZD|ZS|ZH)$", "VCMPE(D|S|H|ZD|ZS|ZH)")>;
H A DARMInstrMVE.td21 // VPT/VCMP restricted predicate for sign invariant types
31 // VPT/VCMP restricted predicate for signed types
41 // VPT/VCMP restricted predicate for unsigned types
51 // VPT/VCMP restricted predicate for floating point
H A DARMInstrInfo.td306 def ARMvcmp : SDNode<"ARMISD::VCMP", SDTARMVCMP>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td787 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
800 def VCMPBFP : VCMP <966, "vcmpbfp $VD, $VA, $VB" , v4f32>;
802 def VCMPEQFP : VCMP <198, "vcmpeqfp $VD, $VA, $VB" , v4f32>;
804 def VCMPGEFP : VCMP <454, "vcmpgefp $VD, $VA, $VB" , v4f32>;
806 def VCMPGTFP : VCMP <710, "vcmpgtfp $VD, $VA, $VB" , v4f32>;
810 def VCMPEQUB : VCMP < 6, "vcmpequb $VD, $VA, $VB" , v16i8>;
812 def VCMPGTSB : VCMP <774, "vcmpgtsb $VD, $VA, $VB" , v16i8>;
814 def VCMPGTUB : VCMP <518, "vcmpgtub $VD, $VA, $VB" , v16i8>;
818 def VCMPEQUH : VCMP < 70, "vcmpequh $VD, $VA, $VB" , v8i16>;
820 def VCMPGTSH : VCMP <838, "vcmpgtsh $VD, $VA, $VB" , v8i16>;
[all …]
H A DREADME_P9.txt9 . Same as other VCMP*, use VCMP/VCMPo form (support intrinsic)
H A DPPCISelLowering.h277 VCMP, enumerator
H A DPPCInstrP10.td1884 def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>;
1885 def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>;
1886 def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>;
H A DP9InstrResources.td217 (instregex "VCMP(EQ|GE|GT)FP(_rec)?$"),
H A DPPCISelLowering.cpp1749 case PPCISD::VCMP: return "PPCISD::VCMP"; in getTargetNodeName()
11116 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), in LowerINTRINSIC_WO_CHAIN()
16393 case PPCISD::VCMP: in PerformDAGCombine()
H A DPPCInstrInfo.td363 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2404 static SDValue combineBallotPattern(SDValue VCMP, bool &Negate) { in combineBallotPattern() argument
2405 assert(VCMP->getOpcode() == AMDGPUISD::SETCC); in combineBallotPattern()
2415 auto VCMP_CC = cast<CondCodeSDNode>(VCMP.getOperand(2))->get(); in combineBallotPattern()
2417 isNullConstant(VCMP.getOperand(1))) { in combineBallotPattern()
2419 auto Cond = VCMP.getOperand(0); in combineBallotPattern()
2449 SDValue VCMP = Cond->getOperand(0); in SelectBRCOND() local
2454 VCMP.getValueType().getSizeInBits() == ST->getWavefrontSize()) { in SelectBRCOND()
2464 if (auto BallotCond = combineBallotPattern(VCMP, NegatedBallot)) { in SelectBRCOND()
2471 Cond = VCMP; in SelectBRCOND()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSkylakeServer.td848 "VCMP(SD|SS)Zrr",
1700 def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
1701 "VCMP(SD|SS)Zrm",
H A DX86SchedIceLake.td863 "VCMP(SD|SS)Zrr",
1715 def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i",
1716 "VCMP(SD|SS)Zrm",
H A DX86InstrAVX512.td2402 // comparison code form (VCMP[EQ/LT/LE/...]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td920 // Section 8.10.14 - VCMP (Vector Compare)