Searched refs:VAddr0Idx (Results 1 – 6 of 6) sorted by relevance
175 int VAddr0Idx = in CheckNSA() local181 const MachineOperand &Op = MI.getOperand(VAddr0Idx + I); in CheckNSA()286 int VAddr0Idx = in runOnMachineFunction() local293 const MachineOperand &Op = MI->getOperand(VAddr0Idx + I); in runOnMachineFunction()
300 int VAddr0Idx = in shrinkMIMG() local340 const MachineOperand &Op = MI.getOperand(VAddr0Idx + Idx); in shrinkMIMG()388 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()389 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef); in shrinkMIMG()390 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()393 MI.removeOperand(VAddr0Idx + 1); in shrinkMIMG()
671 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs() local672 if (VAddr0Idx >= 0) { in getRegs()676 Result.NumVAddrs = RsrcIdx - VAddr0Idx; in getRegs()
464 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getMemOperandsWithOffsetWidth() local465 if (VAddr0Idx >= 0) { in getMemOperandsWithOffsetWidth()467 for (int I = VAddr0Idx; I < SRsrcIdx; ++I) in getMemOperandsWithOffsetWidth()5146 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode, in verifyInstruction() local5171 bool IsNSA = RsrcIdx - VAddr0Idx > 1; in verifyInstruction()5178 VAddrWords = RsrcIdx - VAddr0Idx; in verifyInstruction()5185 VAddrWords = getOpSize(MI, VAddr0Idx) / 4; in verifyInstruction()8729 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getInstSizeInBytes() local8730 if (VAddr0Idx < 0) in getInstSizeInBytes()8734 return 8 + 4 * ((RSrcIdx - VAddr0Idx + 2) / 4); in getInstSizeInBytes()
691 int VAddr0Idx = in getInstruction() local695 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; in getInstruction()696 if (VAddr0Idx >= 0 && NSAArgs > 0) { in getInstruction()701 const unsigned VAddrIdx = VAddr0Idx + 1 + i; in getInstruction()953 int VAddr0Idx = in convertMIMGInst() local1056 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; in convertMIMGInst()1086 MI.erase(MI.begin() + VAddr0Idx + AddrSize, in convertMIMGInst()1087 MI.begin() + VAddr0Idx + Info->VAddrDwords); in convertMIMGInst()
3918 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize() local3925 assert(VAddr0Idx != -1); in validateMIMGAddrSize()3927 assert(SrsrcIdx > VAddr0Idx); in validateMIMGAddrSize()3939 bool IsNSA = SrsrcIdx - VAddr0Idx > 1; in validateMIMGAddrSize()3941 IsNSA ? SrsrcIdx - VAddr0Idx in validateMIMGAddrSize()3942 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()3955 ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize; in validateMIMGAddrSize()