Searched refs:VAddr0Idx (Results 1 – 6 of 6) sorted by relevance
181 int VAddr0Idx = in CheckNSA() local187 const MachineOperand &Op = MI.getOperand(VAddr0Idx + I); in CheckNSA()291 int VAddr0Idx = in run() local298 const MachineOperand &Op = MI->getOperand(VAddr0Idx + I); in run()
311 int VAddr0Idx = in shrinkMIMG() local351 const MachineOperand &Op = MI.getOperand(VAddr0Idx + Idx); in shrinkMIMG()399 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase)); in shrinkMIMG()400 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef); in shrinkMIMG()401 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()404 MI.removeOperand(VAddr0Idx + 1); in shrinkMIMG()
699 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs() local700 if (VAddr0Idx >= 0) { in getRegs()704 Result.NumVAddrs = RsrcIdx - VAddr0Idx; in getRegs()
474 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getMemOperandsWithOffsetWidth() local475 if (VAddr0Idx >= 0) { in getMemOperandsWithOffsetWidth()477 for (int I = VAddr0Idx; I < SRsrcIdx; ++I) in getMemOperandsWithOffsetWidth()5331 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode, in verifyInstruction() local5356 bool IsNSA = RsrcIdx - VAddr0Idx > 1; in verifyInstruction()5363 VAddrWords = RsrcIdx - VAddr0Idx; in verifyInstruction()5370 VAddrWords = getOpSize(MI, VAddr0Idx) / 4; in verifyInstruction()9230 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getInstSizeInBytes() local9231 if (VAddr0Idx < 0) in getInstSizeInBytes()9235 return 8 + 4 * ((RSrcIdx - VAddr0Idx + 2) / 4); in getInstSizeInBytes()
843 int VAddr0Idx = in getInstruction() local847 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; in getInstruction()848 if (VAddr0Idx >= 0 && NSAArgs > 0) { in getInstruction()853 const unsigned VAddrIdx = VAddr0Idx + 1 + i; in getInstruction()1177 int VAddr0Idx = in convertMIMGInst() local1281 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; in convertMIMGInst()1311 MI.erase(MI.begin() + VAddr0Idx + AddrSize, in convertMIMGInst()1312 MI.begin() + VAddr0Idx + Info->VAddrDwords); in convertMIMGInst()
4178 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize() local4186 assert(VAddr0Idx != -1); in validateMIMGAddrSize()4188 assert(SrsrcIdx > VAddr0Idx); in validateMIMGAddrSize()4200 bool IsNSA = SrsrcIdx - VAddr0Idx > 1; in validateMIMGAddrSize()4202 IsNSA ? SrsrcIdx - VAddr0Idx in validateMIMGAddrSize()4203 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()4216 ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize; in validateMIMGAddrSize()