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Searched refs:VALU (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp60 enum DelayType { VALU, TRANS, SALU, OTHER }; enumerator
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
67 return VALU; in getDelayType()
117 case VALU: in DelayInfo()
160 VALUNum += (Type == VALU); in advance()
172 TRANSNumVALU += (Type == VALU); in advance()
H A DSIInstrFormats.td18 field bit VALU = 0;
27 // VALU instruction formats.
160 let TSFlags{1} = VALU;
259 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
275 let VALU = 1;
544 let VALU = 1;
H A DAMDGPUIGroupLP.cpp69 VALU = 1u << 1, enumerator
79 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
1626 SchedGroupMask::VALU, ExpRequirement, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1639 SchedGroupMask::VALU, ExpRequirement, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1679 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1693 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1770 SchedGroupMask::VALU, VALUOps, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1792 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1814 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2167 SchedGroupMask::VALU, 2, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
[all …]
H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
36 // Other quarter rate VALU instructions
74 // FIXME: Should there be a class for instructions which are VALU
75 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
120 def HWTransVALU : ProcResource<1> { // Transcendental VALU
H A DGCNHazardRecognizer.h89 int checkVALUHazards(MachineInstr *VALU);
H A DGCNHazardRecognizer.cpp886 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { in checkVALUHazards() argument
889 if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) { in checkVALUHazards()
892 auto IsTransDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
899 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
916 auto IsShift16BitDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
935 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
964 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
978 if (VALU->readsRegister(AMDGPU::VCC, TRI)) { in checkVALUHazards()
986 switch (VALU->getOpcode()) { in checkVALUHazards()
989 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
[all …]
H A DVOPInstructions.td54 let VALU = 1;
137 let VALU = 1;
175 let VALU = 1;
607 let VALU = 1;
628 let VALU = 1;
661 let VALU = 1;
822 let VALU = 1;
862 let VALU = 1;
904 let VALU = 1;
993 let VALU = 1;
H A DVOPDInstructions.td78 let VALU = 1;
H A DSIDefines.h56 VALU = 1 << 1, enumerator
H A DSIInstrInfo.h417 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
421 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
H A DSIInstructions.td804 let VALU = 1;
862 let VALU = 1;
882 let VALU = 1;
937 let Spill = 1, VALU = 1, isConvergent = 1 in {
957 } // End Spill = 1, VALU = 1, isConvergent = 1
963 let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
989 } // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
2611 // will be moved to the VALU.
2853 // Handle the VALU case.
H A DFLATInstructions.td104 let VALU = ps.VALU;
169 let VALU = ps.VALU;
304 let VALU = 1;
485 let VALU = 1;
H A DBUFInstructions.td354 let VALU = ps.VALU;
514 let VALU = isLds;
680 let VALU = 1;
2432 let VALU = ps.VALU;
H A DVOP1Instructions.td57 let VALU = 1;
68 let VALU = 1;
H A DVOPCInstructions.td151 let VALU = 1;
163 let VALU = 1;
H A DSIInstrInfo.td1172 // 32-bit VALU immediate operand that uses the constant bus.
1175 // 32-bit VALU immediate operand with a 16-bit value that uses the
H A DVOP2Instructions.td77 let VALU = 1;
88 let VALU = 1;
H A DAMDGPU.td95 "Have VALU add/sub instructions without carry out"
H A DVOP3Instructions.td459 // Only use VALU ops when the result is divergent.
H A DSOPInstructions.td777 // Use added complexity so these patterns are preferred to the VALU patterns.
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td456 let PPC970_Unit = 5 in { // VALU Operations.
858 } // VALU Operations.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td290 // MASK = 0x0000 0002: VALU instructions may be scheduled across SCHED_BARRIER.