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Searched refs:VALU (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp66 enum DelayType { VALU, TRANS, SALU, OTHER }; enumerator
72 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
73 return VALU; in getDelayType()
123 case VALU: in DelayInfo()
165 VALUNum += (Type == VALU); in advance()
177 TRANSNumVALU += (Type == VALU); in advance()
H A DAMDGPUWaitSGPRHazards.cpp118 static constexpr unsigned VALU = (1 << 1); member
248 State.VCCHazard &= ~HazardState::VALU; in runOnMachineBasicBlock()
319 if (State.VCCHazard & HazardState::VALU) in runOnMachineBasicBlock()
335 if (State.VCCHazard & HazardState::VALU) in runOnMachineBasicBlock()
341 State.VCCHazard = IsSALU ? HazardState::SALU : HazardState::VALU; in runOnMachineBasicBlock()
366 if (State.VCCHazard & HazardState::VALU) in runOnMachineBasicBlock()
392 State.VCCHazard &= ~HazardState::VALU; in runOnMachineBasicBlock()
H A DSIInstrFormats.td18 field bit VALU = 0;
27 // VALU instruction formats.
164 let TSFlags{1} = VALU;
264 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
280 let VALU = 1;
560 let VALU = 1;
H A DAMDGPUIGroupLP.cpp68 VALU = 1u << 1, enumerator
78 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
1589 SchedGroupMask::VALU, ExpRequirement, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1602 SchedGroupMask::VALU, ExpRequirement, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1642 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1656 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1733 SchedGroupMask::VALU, VALUOps, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1755 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
1777 SchedGroupMask::VALU, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
2165 SchedGroupMask::VALU, 2, PipelineSyncID, DAG, TII); in applyIGLPStrategy()
[all …]
H A DGCNHazardRecognizer.cpp926 static bool consumesDstSelForwardingOperand(const MachineInstr *VALU, in consumesDstSelForwardingOperand() argument
939 for (auto &Operand : VALU->operands()) { in consumesDstSelForwardingOperand()
947 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { in checkVALUHazards() argument
950 if (ST.hasTransForwardingHazard() && !SIInstrInfo::isTRANS(*VALU)) { in checkVALUHazards()
953 auto IsTransDefFn = [this, VALU](const MachineInstr &MI) { in checkVALUHazards()
960 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
977 auto IsShift16BitDefFn = [this, VALU](const MachineInstr &ProducerMI) { in checkVALUHazards()
982 return consumesDstSelForwardingOperand(VALU, ForwardedDst, TRI); in checkVALUHazards()
988 if (consumesDstSelForwardingOperand(VALU, &Def, TRI)) in checkVALUHazards()
1016 for (const MachineOperand &Use : VALU->explicit_uses()) { in checkVALUHazards()
[all …]
H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
36 // Other quarter rate VALU instructions
75 // FIXME: Should there be a class for instructions which are VALU
76 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
123 def HWTransVALU : ProcResource<1> { // Transcendental VALU
H A DGCNHazardRecognizer.h89 int checkVALUHazards(MachineInstr *VALU);
H A DVOPInstructions.td58 let VALU = 1;
140 let VALU = 1;
176 let VALU = 1;
735 let VALU = 1;
755 let VALU = 1;
789 let VALU = 1;
977 let VALU = 1;
1014 let VALU = 1;
1058 let VALU = 1;
1178 let VALU = 1;
H A DSIDefines.h57 VALU = 1 << 1, enumerator
H A DVOPDInstructions.td119 let VALU = 1;
H A DSIInstrInfo.h436 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
440 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
H A DSIInstructions.td881 let VALU = 1;
939 let VALU = 1;
959 let VALU = 1;
1014 let Spill = 1, VALU = 1, isConvergent = 1 in {
1036 } // End Spill = 1, VALU = 1, isConvergent = 1
1043 let UseNamedOperandTable = 1, Spill = 1, VALU = 1,
1073 } // End UseNamedOperandTable = 1, Spill = 1, VALU = 1, SchedRW = [WriteVMEM]
2811 // will be moved to the VALU.
3076 // Handle the VALU case.
H A DFLATInstructions.td112 let VALU = ps.VALU;
178 let VALU = ps.VALU;
360 let VALU = 1;
606 let VALU = 1;
H A DBUFInstructions.td357 let VALU = ps.VALU;
518 let VALU = isLds;
673 let VALU = 1;
2426 let VALU = ps.VALU;
H A DVOP1Instructions.td57 let VALU = 1;
68 let VALU = 1;
H A DSIInstrInfo.td1316 // 32-bit VALU immediate operand that uses the constant bus.
1319 // 32-bit VALU immediate operand with a 16-bit value that uses the
1323 // 64-bit VALU immediate operand that uses the constant bus.
H A DVOP2Instructions.td91 let VALU = 1;
102 let VALU = 1;
H A DVOPCInstructions.td236 let VALU = 1;
248 let VALU = 1;
H A DAMDGPU.td95 "Have VALU add/sub instructions without carry out"
H A DMIMGInstructions.td2035 let VALU = 1;
H A DVOP3Instructions.td530 // Only use VALU ops when the result is divergent.
H A DSOPInstructions.td756 // Use added complexity so these patterns are preferred to the VALU patterns.
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td456 let PPC970_Unit = 5 in { // VALU Operations.
858 } // VALU Operations.
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td1417 // Pass SiFive7VA for VA1 and VA1OrVA2 if there is only 1 VALU.
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td317 // MASK = 0x0000 0002: VALU instructions may be scheduled across SCHED_BARRIER.