Searched refs:V2Q (Results 1 – 6 of 6) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 1147 return DAG.getNode(HexagonISD::V2Q, dl, VecTy, ByteVec); in buildHvxVectorPred() 1251 return DAG.getNode(HexagonISD::V2Q, dl, ty(VecV), InsV); in insertHvxElementPred() 1322 return DAG.getNode(HexagonISD::V2Q, dl, ResTy, ShuffV); in extractHvxSubvectorPred() 1488 return DAG.getNode(HexagonISD::V2Q, dl, VecTy, ByteVec); in insertHvxSubvectorPred() 1757 return DAG.getNode(HexagonISD::V2Q, dl, VecTy, Res); in LowerHvxConcatVectors() 2030 return DAG.getNode(HexagonISD::V2Q, dl, ResTy, I2V); in LowerHvxBitcast() 2061 return DAG.getNode(HexagonISD::V2Q, dl, ResTy, S); in LowerHvxSelect() 2220 VectorPair MaskU = {DAG.getNode(HexagonISD::V2Q, dl, BoolTy, Tmp.first), in LowerHvxMaskedOp() 2221 DAG.getNode(HexagonISD::V2Q, dl, BoolTy, Tmp.second)}; in LowerHvxMaskedOp() 3613 case HexagonISD::V2Q in PerformHvxDAGCombine() [all...] |
H A D | HexagonPatternsHVX.td | 771 def V2Q: OutPatFrag<(ops node:$Vs), (V6_vandvrt $Vs, (ToI32 -1))>; 775 (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>; 777 (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>; 779 (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>;
|
H A D | HexagonISelLowering.h | 85 V2Q, // Convert HVX vector to a vector predicate reg. [*] enumerator
|
H A D | HexagonISelDAGToDAG.cpp | 1048 case HexagonISD::V2Q: return SelectV2Q(N); in Select()
|
H A D | HexagonISelLowering.cpp | 1948 case HexagonISD::V2Q: return "HexagonISD::V2Q"; in getTargetNodeName()
|
/freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 21733 auto V2Q = [this, VecLen] (llvm::Value *Vec) { in EmitHexagonBuiltinExpr() local 21758 llvm::Value *PredIn = V2Q(Builder.CreateLoad(PredAddr)); in EmitHexagonBuiltinExpr() 21801 Ops.push_back(V2Q(EmitScalarExpr(PredOp))); in EmitHexagonBuiltinExpr()
|