| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConv.td | 116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
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| H A D | HexagonRegisterInfo.cpp | 81 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, in getCallerSavedRegs()
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| H A D | HexagonRegisterInfo.td | 237 def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>;
257 def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>;
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am642-evm-icssg1-dualemac.dtso | 44 AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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| H A D | k3-am642-evm-icssg1-dualemac-mii.dtso | 70 AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */
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| H A D | k3-am642-sk.dts | 325 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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| H A D | k3-am642-evm.dts | 382 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
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| H A D | k3-am642-tqma64xxl-mbax4xxl.dts | 923 /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 144 V11, V12, V13]>>>>,
153 V11, V12, V13]>>>>,
268 V8, V9, V10, V11, V12, V13]>>>,
273 V8, V9, V10, V11, V12, V13]>>>,
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| H A D | PPCRegisterInfo.td | 421 (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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| H A D | PPCISelLowering.cpp | 4521 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_64SVR4()
4979 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in needStackSlotPassParameters()
6270 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_64SVR4()
6870 PPC::V10, PPC::V11, PPC::V12, PPC::V13}; in CC_AIX()
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| /freebsd/sys/contrib/device-tree/src/arm/gemini/ |
| H A D | gemini-nas4220b.dts | 126 pins = "V11 GMAC1 TXC";
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| H A D | gemini-sq201.dts | 213 pins = "V11 GMAC1 TXC";
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| H A D | gemini-sl93512r.dts | 193 pins = "V11 GMAC1 TXEN";
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| H A D | gemini-dlink-dns-313.dts | 251 pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
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| H A D | gemini-dlink-dir-685.dts | 404 "U8 GMAC0 TXC", "V11 GMAC1 TXC",
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 109 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 100 VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2801 const APInt &V11 = CI11->getValue(); in instCombineIntrinsic() local
2802 APInt Len = V11.zextOrTrunc(6); in instCombineIntrinsic()
2803 APInt Idx = V11.lshr(8).zextOrTrunc(6); in instCombineIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 590 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, in DecodeHvxVRRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstructions.td | 2418 defm : SI_INDIRECT_Pattern <v11f32, f32, "V11">;
2428 defm : SI_INDIRECT_Pattern <v11i32, i32, "V11">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18903 RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
20817 .Case("{v11}", RISCV::V11) in getRegForInlineAsmConstraint()
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