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Searched refs:UsedRegs (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp61 LiveRegUnits UsedRegs(*RegInfo); in copyPhysReg() local
62 UsedRegs.addLiveOuts(MBB); in copyPhysReg()
68 UsedRegs.stepBackward(*--InstUpToI); in copyPhysReg()
70 if (UsedRegs.available(ARM::CPSR)) { in copyPhysReg()
84 if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) { in copyPhysReg()
88 if (UsedRegs.available(Reg)) { in copyPhysReg()
H A DThumb1FrameLowering.cpp585 const LiveRegUnits &UsedRegs, unsigned &PopReg, in findTemporariesForLR() argument
589 if (UsedRegs.available(Reg)) { in findTemporariesForLR()
657 LiveRegUnits UsedRegs(TRI); in emitPopSpecialFixUp() local
658 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
665 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
674 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
693 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg, in emitPopSpecialFixUp()
704 UsedRegs.stepBackward(*PrevMBBI); in emitPopSpecialFixUp()
705 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, in emitPopSpecialFixUp()
H A DARMFastISel.cpp250 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2083 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, in FinishCall() argument
2110 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2111 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2129 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2350 SmallVector<Register, 4> UsedRegs; in ARMEmitLibcall() local
2351 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2354 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2495 SmallVector<Register, 4> UsedRegs; in SelectCall() local
2496 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
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H A DARMLoadStoreOptimizer.cpp865 DenseSet<unsigned> UsedRegs; in MergeOpsUpdate() local
874 UsedRegs.insert(Reg); in MergeOpsUpdate()
966 if (UsedRegs.count(MO.getReg())) in MergeOpsUpdate()
/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp159 SmallVectorImpl<unsigned> &UsedRegs) { in addRegisterReadWrite() argument
166 PRF.addRegisterWrite(WriteRef(SourceIndex, &WS), UsedRegs); in addRegisterReadWrite()
179 const InstRef &IR, unsigned Ops, ArrayRef<unsigned> UsedRegs) { in notifyInstructionDispatched() argument
181 HWInstructionDispatchedEvent(IR, UsedRegs, Ops)); in notifyInstructionDispatched()
227 SmallVector<unsigned, 4> UsedRegs(PRF.getNumRegisterFiles()); in tryIssue() local
228 addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs); in tryIssue()
231 notifyInstructionDispatched(IR, NumMicroOps, UsedRegs); in tryIssue()
H A DDispatchStage.cpp38 ArrayRef<unsigned> UsedRegs, in notifyInstructionDispatched() argument
42 HWInstructionDispatchedEvent(IR, UsedRegs, UOps)); in notifyInstructionDispatched()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LowerTileCopy.cpp87 LiveRegUnits UsedRegs(*TRI); in runOnMachineFunction() local
88 UsedRegs.addLiveOuts(MBB); in runOnMachineFunction()
90 UsedRegs.stepBackward(MI); in runOnMachineFunction()
110 if (UsedRegs.available(RegT)) { in runOnMachineFunction()
H A DX86CallFrameOptimization.cpp115 const DenseSet<MCRegister> &UsedRegs);
280 const X86RegisterInfo &RegInfo, const DenseSet<MCRegister> &UsedRegs) { in classifyInstruction() argument
343 for (MCRegister U : UsedRegs) in classifyInstruction()
407 DenseSet<MCRegister> UsedRegs; in collectCallInfo() local
413 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
456 UsedRegs.insert(Reg.asMCReg()); in collectCallInfo()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp39 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
64 UsedRegs[(*AI).id() / 32] |= 1 << ((*AI).id() & 31); in MarkAllocated()
69 UsedRegs[(*AI).id() / 32] &= ~(1 << ((*AI).id() & 31)); in MarkUnallocated()
H A DWindowScheduler.cpp648 SmallVector<Register, 128> UsedRegs; in updateLiveIntervals() local
654 if (!is_contained(UsedRegs, Reg)) in updateLiveIntervals()
655 UsedRegs.push_back(Reg); in updateLiveIntervals()
657 Context->LIS->repairIntervalsInRange(MBB, MBB->begin(), MBB->end(), UsedRegs); in updateLiveIntervals()
H A DMachineBasicBlock.cpp1212 SmallVector<Register, 4> UsedRegs; in SplitCriticalEdge() local
1221 if (!is_contained(UsedRegs, Reg)) in SplitCriticalEdge()
1222 UsedRegs.push_back(Reg); in SplitCriticalEdge()
1355 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); in SplitCriticalEdge()
H A DPrologEpilogInserter.cpp1230 BitVector UsedRegs(TRI.getNumRegs()); in insertZeroCallUsedRegs() local
1245 UsedRegs.set(Reg.id()); in insertZeroCallUsedRegs()
1265 if (OnlyUsed && !UsedRegs[Reg.id()]) in insertZeroCallUsedRegs()
H A DMachineInstr.cpp2270 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, in setPhysRegsDeadExcept() argument
2283 if (llvm::none_of(UsedRegs, in setPhysRegsDeadExcept()
2291 for (const Register &UsedReg : UsedRegs) in setPhysRegsDeadExcept()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp1158 SmallVector<Register, 8> UsedRegs; in EmitMachineNode() local
1167 UsedRegs.push_back(Reg); in EmitMachineNode()
1176 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
1184 append_range(UsedRegs, MCID.implicit_uses()); in EmitMachineNode()
1191 UsedRegs.push_back(Reg); in EmitMachineNode()
1199 llvm::append_range(UsedRegs, RCRegs); in EmitMachineNode()
1203 if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef()) in EmitMachineNode()
1204 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
H A DInOrderIssueStage.h106 ArrayRef<unsigned> UsedRegs);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DVarLocBasedImpl.cpp885 SmallVectorImpl<Register> &UsedRegs) const;
1239 SmallVectorImpl<Register> &UsedRegs) const { in getUsedRegs()
1252 assert((UsedRegs.empty() || FoundReg != UsedRegs.back()) && in getUsedRegs()
1254 UsedRegs.push_back(FoundReg); in getUsedRegs()
1619 SmallVector<Register, 32> UsedRegs; in transferRegisterDef() local
1620 getUsedRegs(OpenRanges.getVarLocs(), UsedRegs); in transferRegisterDef()
1621 for (Register Reg : UsedRegs) { in transferRegisterDef()
H A DInstrRefBasedImpl.cpp2408 BitVector UsedRegs(TRI->getNumRegs()); in produceMLocTransferFunction() local
2414 UsedRegs.set(ID); in produceMLocTransferFunction()
2423 BV &= UsedRegs; in produceMLocTransferFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h185 SmallVector<uint32_t, 16> UsedRegs; variable
258 return UsedRegs[Reg.id() / 32] & (1 << (Reg.id() & 31)); in isAllocated()
H A DMachineInstr.h1730 LLVM_ABI void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp4453 static Register tryScavengeRegister(LiveRegUnits const &UsedRegs, in tryScavengeRegister() argument
4456 if (PreferredReg != AArch64::NoRegister && UsedRegs.available(PreferredReg)) in tryScavengeRegister()
4459 if (UsedRegs.available(Reg)) in tryScavengeRegister()
4492 LiveRegUnits const &UsedRegs, in ScopedScavengeOrSpill()
4499 FreeReg = tryScavengeRegister(UsedRegs, AllocatableRegs, PreferredReg); in ScopedScavengeOrSpill()
4572 LiveRegUnits const &UsedRegs, in expandSpillPPRToZPRSlotPseudo() argument
4580 MF, MBB, MI, AArch64::Z0, AArch64::ZPRRegClass, UsedRegs, SR.ZPRRegs, in expandSpillPPRToZPRSlotPseudo()
4616 LiveRegUnits const &UsedRegs, ScavengeableRegs const &SR, in expandFillPPRFromZPRSlotPseudo() argument
4623 MF, MBB, MI, AArch64::Z0, AArch64::ZPRRegClass, UsedRegs, SR.ZPRRegs, in expandFillPPRFromZPRSlotPseudo()
4627 MF, MBB, MI, AArch64::P0, AArch64::PPR_3bRegClass, UsedRegs, SR.PPR3bRegs, in expandFillPPRFromZPRSlotPseudo()
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