| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 260 Register UseReg; in addLinkerOpt() member
304 Pair.UseReg = BBI->getOperand(0).getReg(); in addLinkerOpt()
322 if (BBI->readsRegister(Pair->UseReg, TRI) || in addLinkerOpt()
323 BBI->modifiesRegister(Pair->UseReg, TRI)) { in addLinkerOpt()
339 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
341 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
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| H A D | PPCVSXSwapRemoval.cpp | 724 Register UseReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
725 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs()
801 Register UseReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
802 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
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| H A D | PPCMIPeephole.cpp | 1295 for (auto UseReg : ToErase->explicit_uses()) in simplifyCode() local
1296 if (UseReg.isReg()) in simplifyCode()
1297 addRegToUpdate(UseReg.getReg()); in simplifyCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StackTaggingPreRA.cpp | 275 Register UseReg = WorkList.pop_back_val(); in findFirstSlotCandidate()
276 for (auto &UseI : MRI->use_instructions(UseReg)) { in findFirstSlotCandidate() local
291 << Register::virtReg2Index(UseReg) << " in " << UseI in findFirstSlotCandidate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 243 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, in isUnsafeToMoveAcross() argument
246 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
252 static Register UseReg(const MachineOperand& MO) { in UseReg() function
263 Register I2UseReg = UseReg(I2.getOperand(1)); in isSafeToMoveTogether()
330 Register I1UseReg = UseReg(I1.getOperand(1)); in isSafeToMoveTogether()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 94 Register UseReg, uint8_t OpTy) const;
659 Register UseReg, uint8_t OpTy) const { in getRegSeqInit() argument
660 MachineInstr *Def = MRI->getVRegDef(UseReg); in getRegSeqInit()
709 Register UseReg = OpToFold.getReg(); in tryToFoldACImm() local
710 if (!UseReg.isVirtual()) in tryToFoldACImm()
717 MachineInstr *Def = MRI->getVRegDef(UseReg); in tryToFoldACImm()
729 if (!getRegSeqInit(Defs, UseReg, OpTy)) in tryToFoldACImm()
894 Register UseReg = OpToFold.getReg(); in foldOperand() local
895 UseMI->getOperand(1).setReg(UseReg); in foldOperand()
910 getRegSeqInit(Defs, UseReg, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
[all …]
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| H A D | GCNHazardRecognizer.cpp | 957 Register UseReg; in checkVALUHazards() local
958 auto IsVALUDefSGPRFn = [&UseReg, TRI](const MachineInstr &MI) { in checkVALUHazards()
961 return MI.modifiesRegister(UseReg, TRI); in checkVALUHazards()
968 UseReg = Use.getReg(); in checkVALUHazards()
969 if (TRI->isSGPRReg(MRI, UseReg)) { in checkVALUHazards()
979 UseReg = AMDGPU::VCC; in checkVALUHazards()
990 UseReg = Src->getReg(); in checkVALUHazards()
998 UseReg = AMDGPU::EXEC; in checkVALUHazards()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 724 unsigned UseReg = MO.getReg(); in getMachineOpValue() local
748 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { in getMachineOpValue()
767 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2); in getMachineOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 206 unsigned ARMSelectCallOp(bool UseReg);
2174 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { in ARMSelectCallOp() argument
2175 if (UseReg) in ARMSelectCallOp()
2388 bool UseReg = false; in SelectCall() local
2390 if (!GV || Subtarget->genLongCalls()) UseReg = true; in SelectCall()
2393 if (UseReg) { in SelectCall()
2403 unsigned CallOpc = ARMSelectCallOp(UseReg); in SelectCall()
2410 if (UseReg) { in SelectCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ScheduleDAGInstrs.cpp | 272 Register UseReg = UseInstr->getOperand(UseOpIdx).getReg(); in addPhysRegDataDeps() local
275 !UseMIDesc.hasImplicitUseOfPhysReg(UseReg); in addPhysRegDataDeps()
277 Dep = SDep(SU, SDep::Data, UseReg); in addPhysRegDataDeps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 918 Register UseReg = SubsequentUse->getReg(); in runOnMachineFunction() local
920 if (DefReg != UseReg || !MRI.hasOneNonDBGUse(DefReg)) in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 403 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
406 let Uses = [UseReg];
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| H A D | MipsInstrInfo.td | 1728 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1731 let Uses = [UseReg];
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