| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankSelect.cpp | 274 Register UseReg = getVReg(UseOP); in runOnMachineFunction() local
275 if (!UseReg.isValid()) in runOnMachineFunction()
279 if (!MRI.getRegClassOrNull(UseReg) || in runOnMachineFunction()
280 MRI.getVRegDef(UseReg)->isPreISelOpcode()) in runOnMachineFunction()
284 const RegisterBank *RB = RBSHelper.getRegBankToAssign(UseReg); in runOnMachineFunction()
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| H A D | SIFoldOperands.cpp | 228 Register UseReg) const;
961 Register UseReg) const { in getRegSeqInit()
962 MachineInstr *Def = MRI->getVRegDef(UseReg); in getRegSeqInit()
1110 Register UseReg = OpToFold.getReg(); in tryToFoldACImm() local
1111 if (!UseReg.isVirtual()) in tryToFoldACImm()
1119 MachineInstr *Def = MRI->getVRegDef(UseReg); in tryToFoldACImm()
1309 Register UseReg = OpToFold.getReg(); in foldOperand() local
1310 UseMI->getOperand(1).setReg(UseReg); in foldOperand()
1327 TRI->isSGPRReg(*MRI, UseReg)) { in foldOperand()
1334 TRI->getCoveringSubRegIndexes(TRI->getRegClassForReg(*MRI, UseReg), M, in foldOperand()
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| H A D | GCNHazardRecognizer.cpp | 1009 Register UseReg; in checkVALUHazards() local
1010 auto IsVALUDefSGPRFn = [&UseReg, TRI](const MachineInstr &MI) { in checkVALUHazards()
1013 return MI.modifiesRegister(UseReg, TRI); in checkVALUHazards()
1020 UseReg = Use.getReg(); in checkVALUHazards()
1021 if (TRI->isSGPRReg(MRI, UseReg)) { in checkVALUHazards()
1031 UseReg = AMDGPU::VCC; in checkVALUHazards()
1042 UseReg = Src->getReg(); in checkVALUHazards()
1050 UseReg = AMDGPU::EXEC; in checkVALUHazards()
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| H A D | AMDGPURegBankLegalizeHelper.cpp | 995 Register UseReg = MI.getOperand(i).getReg(); in applyMappingPHI() local
997 auto DefMI = MRI.getVRegDef(UseReg)->getIterator(); in applyMappingPHI()
1002 auto NewUse = B.buildAnyExt(SgprRB_S32, UseReg); in applyMappingPHI()
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| H A D | GCNSchedStrategy.cpp | 1948 Register UseReg = MO.getReg(); in rematerialize() local
1949 if (!UseReg.isVirtual()) in rematerialize()
1952 LiveInterval &LI = DAG.LIS->getInterval(UseReg); in rematerialize()
1957 LaneBitmask LiveInMask = RegionLiveIns.at(UseReg); in rematerialize()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 256 Register UseReg; in addLinkerOpt() member
300 Pair.UseReg = BBI->getOperand(0).getReg(); in addLinkerOpt()
318 if (BBI->readsRegister(Pair->UseReg, TRI) || in addLinkerOpt()
319 BBI->modifiesRegister(Pair->UseReg, TRI)) { in addLinkerOpt()
335 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
337 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
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| H A D | PPCVSXSwapRemoval.cpp | 722 Register UseReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
723 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs()
799 Register UseReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
800 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
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| H A D | PPCMIPeephole.cpp | 1299 for (auto UseReg : ToErase->explicit_uses()) in simplifyCode() local
1300 if (UseReg.isReg()) in simplifyCode()
1301 addRegToUpdate(UseReg.getReg()); in simplifyCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StackTaggingPreRA.cpp | 269 Register UseReg = WorkList.pop_back_val(); in findFirstSlotCandidate() local
270 for (auto &UseI : MRI->use_instructions(UseReg)) { in findFirstSlotCandidate()
285 << printReg(UseReg) << " in " << UseI << "\n"); in findFirstSlotCandidate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 236 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, in isUnsafeToMoveAcross() argument
239 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
245 static Register UseReg(const MachineOperand& MO) { in UseReg() function
256 Register I2UseReg = UseReg(I2.getOperand(1)); in isSafeToMoveTogether()
323 Register I1UseReg = UseReg(I1.getOperand(1)); in isSafeToMoveTogether()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 751 MCRegister UseReg = MO.getReg(); in getMachineOpValue() local
775 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { in getMachineOpValue()
794 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2); in getMachineOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 231 unsigned ARMSelectCallOp(bool UseReg);
2237 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { in ARMSelectCallOp() argument
2238 if (UseReg) in ARMSelectCallOp()
2454 bool UseReg = false; in SelectCall() local
2456 if (!GV || Subtarget->genLongCalls()) UseReg = true; in SelectCall()
2459 if (UseReg) { in SelectCall()
2470 unsigned CallOpc = ARMSelectCallOp(UseReg); in SelectCall()
2477 if (UseReg) { in SelectCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ScheduleDAGInstrs.cpp | 293 Register UseReg = UseInstr->getOperand(UseOpIdx).getReg(); in addPhysRegDataDeps() local
296 !UseMIDesc.hasImplicitUseOfPhysReg(UseReg); in addPhysRegDataDeps()
298 Dep = SDep(SU, SDep::Data, UseReg); in addPhysRegDataDeps()
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| H A D | MachineSink.cpp | 1823 RegSubRegPair &UseReg = Entry.first; in aggressivelySinkIntoCycle() local
1824 MI->substituteRegister(UseReg.Reg, NewMI->getOperand(0).getReg(), in aggressivelySinkIntoCycle()
1825 UseReg.SubReg, *TRI); in aggressivelySinkIntoCycle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 959 Register UseReg = SubsequentUse->getReg(); in runOnMachineFunction() local
961 if (DefReg != UseReg || in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 403 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
406 let Uses = [UseReg];
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| H A D | MipsInstrInfo.td | 1740 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1743 let Uses = [UseReg];
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