Searched refs:UseRC (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineSSAUpdater.cpp | 243 const TargetRegisterClass *UseRC = in RewriteUse() local
245 if (UseRC && !MRI->constrainRegClass(NewVR, UseRC)) { in RewriteUse()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 101 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local
106 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
135 if (!UseRC) in EmitCopyFromReg()
136 UseRC = RC; in EmitCopyFromReg()
139 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg()
143 UseRC = ComRC; in EmitCopyFromReg()
159 } else if (UseRC) { in EmitCopyFromReg()
160 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg()
162 DstRC = UseRC; in EmitCopyFromReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 450 const TargetRegisterClass *UseRC = in PPCEmitLoad() local
458 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
478 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
497 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad()
498 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad()
508 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
2425 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local
2429 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm); in fastEmitInst_ri()
2438 const TargetRegisterClass *UseRC = in fastEmitInst_r() local
2442 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0); in fastEmitInst_r()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 1822 const TargetRegisterClass *UseRC = in foldCopyToAGPRRegSequence() local
1901 TRI->getSubRegisterClass(UseRC, DestSubIdx); in foldCopyToAGPRRegSequence()
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