Searched refs:UseRC (Results 1 – 4 of 4) sorted by relevance
243 const TargetRegisterClass *UseRC = in RewriteUse() local245 if (UseRC && !MRI->constrainRegClass(NewVR, UseRC)) { in RewriteUse()
102 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()136 if (!UseRC) in EmitCopyFromReg()137 UseRC = RC; in EmitCopyFromReg()140 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg()144 UseRC = ComRC; in EmitCopyFromReg()160 } else if (UseRC) { in EmitCopyFromReg()161 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg()163 DstRC = UseRC; in EmitCopyFromReg()
462 const TargetRegisterClass *UseRC = in PPCEmitLoad() local470 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()490 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()509 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad()510 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad()520 ResultReg = createResultReg(UseRC); in PPCEmitLoad()2433 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local2437 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm); in fastEmitInst_ri()2446 const TargetRegisterClass *UseRC = in fastEmitInst_r() local2450 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0); in fastEmitInst_r()[all …]
1085 const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg); in foldOperand() local1086 if (AMDGPU::getRegBitWidth(*UseRC) != 64) in foldOperand()