| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 233 bool tryFoldRegSeqSplat(MachineInstr *UseMI, unsigned UseOpIdx,
238 unsigned UseOpIdx,
240 void foldOperand(FoldableDef OpToFold, MachineInstr *UseMI, int UseOpIdx,
1038 MachineInstr *UseMI, unsigned UseOpIdx, int64_t SplatVal, in tryFoldRegSeqSplat() argument
1041 if (UseOpIdx >= Desc.getNumOperands()) in tryFoldRegSeqSplat()
1045 if (!AMDGPU::isSISrcOperand(Desc, UseOpIdx)) in tryFoldRegSeqSplat()
1048 int16_t RCID = Desc.operands()[UseOpIdx].RegClass; in tryFoldRegSeqSplat()
1061 uint8_t OpTy = Desc.operands()[UseOpIdx].OperandType; in tryFoldRegSeqSplat()
1079 if (!TII->isOperandLegal(*UseMI, UseOpIdx, &TmpOp)) in tryFoldRegSeqSplat()
1086 const FoldableDef &OpToFold, MachineInstr *UseMI, unsigned UseOpIdx, in tryToFoldACImm() argument
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| H A D | GCNSubtarget.cpp | 541 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, in adjustSchedDependency() argument
581 DefI, DefOpIdx, UseI, UseOpIdx)); in adjustSchedDependency()
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| H A D | GCNSubtarget.h | 1690 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
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| H A D | SIInstrInfo.cpp | 5272 unsigned UseOpIdx; in verifyInstruction() local
5273 if (!MI.isRegTiedToUseOperand(StaticNumOps, &UseOpIdx) || in verifyInstruction()
5274 UseOpIdx != StaticNumOps + 1) { in verifyInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | InitUndef.cpp | 230 unsigned UseOpIdx; in processBasicBlock() local
231 if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) { in processBasicBlock()
232 MachineOperand &UseMO = MI.getOperand(UseOpIdx); in processBasicBlock()
235 TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF); in processBasicBlock()
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| H A D | ScheduleDAGInstrs.cpp | 282 int UseOpIdx = I->OpIdx; in addPhysRegDataDeps() local
285 if (UseOpIdx < 0) { in addPhysRegDataDeps()
293 Register UseReg = UseInstr->getOperand(UseOpIdx).getReg(); in addPhysRegDataDeps()
295 ImplicitPseudoUse = UseOpIdx >= ((int)UseMIDesc.getNumOperands()) && in addPhysRegDataDeps()
302 UseInstr, UseOpIdx)); in addPhysRegDataDeps()
306 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep, &SchedModel); in addPhysRegDataDeps()
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| H A D | RegisterCoalescer.cpp | 867 unsigned UseOpIdx; in removeCopyByCommutingDef() local
868 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
881 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx)) in removeCopyByCommutingDef()
915 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx); in removeCopyByCommutingDef()
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| H A D | MachineVerifier.cpp | 2448 unsigned UseOpIdx; in visitMachineInstrBefore() local
2449 if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) { in visitMachineInstrBefore()
2453 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) { in visitMachineInstrBefore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.cpp | 549 SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, in adjustSchedDependency() argument
573 Register Reg = UseMI->getOperand(UseOpIdx).getReg(); in adjustSchedDependency()
577 UseOpIdx = Op.getOperandNo(); in adjustSchedDependency()
584 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx)); in adjustSchedDependency()
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| H A D | AArch64Subtarget.h | 347 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1661 unsigned *UseOpIdx = nullptr) const {
1665 if (UseOpIdx)
1666 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1673 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1675 const MachineOperand &MO = getOperand(UseOpIdx);
1679 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
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| H A D | TargetSubtargetInfo.h | 252 int UseOpIdx, SDep &Dep, in adjustSchedDependency() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.h | 325 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInsertVSETVLI.cpp | 118 unsigned UseOpIdx; in hasUndefinedPassthru() local
119 if (!MI.isRegTiedToUseOperand(0, &UseOpIdx)) in hasUndefinedPassthru()
126 const MachineOperand &UseMO = MI.getOperand(UseOpIdx); in hasUndefinedPassthru()
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| H A D | RISCVInstrInfo.cpp | 3028 unsigned UseOpIdx; in verifyInstruction() local
3029 if (!MI.isRegTiedToUseOperand(0, &UseOpIdx)) { in verifyInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3328 int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, TRI, false); in replaceInstrOperandWithImm() local
3329 if (UseOpIdx >= 0) { in replaceInstrOperandWithImm()
3330 MachineOperand &MO = MI.getOperand(UseOpIdx); in replaceInstrOperandWithImm()
3339 MI.removeOperand(UseOpIdx); in replaceInstrOperandWithImm()
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