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Searched refs:UnitSize (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/DWARFLinkerParallel/
H A DDWARFLinkerUnit.h
/freebsd/contrib/llvm-project/llvm/lib/DWARFLinker/Parallel/
H A DDWARFLinkerUnit.h41 uint64_t getUnitSize() const { return UnitSize; } in getUnitSize()
81 UnitSize = getDebugInfoHeaderSize() + OutUnitDIE->getSize(); in setOutUnitDIE()
186 uint64_t UnitSize = 0; variable
/freebsd/contrib/llvm-project/compiler-rt/lib/fuzzer/
H A DFuzzerLoop.cpp180 size_t UnitSize = CurrentUnitSize; in DumpCurrentUnit() local
181 if (UnitSize <= kMaxUnitSizeToPrint) { in DumpCurrentUnit()
182 PrintHexArray(CurrentUnitData, UnitSize, "\n"); in DumpCurrentUnit()
183 PrintASCII(CurrentUnitData, UnitSize, "\n"); in DumpCurrentUnit()
185 WriteUnitToFileWithPrefix({CurrentUnitData, CurrentUnitData + UnitSize}, in DumpCurrentUnit()
H A DFuzzerFork.cpp243 size_t UnitSize = U.size(); in RunOneMergeJob() local
245 std::upper_bound(FilesSizes.begin(), FilesSizes.end(), UnitSize) - in RunOneMergeJob()
247 FilesSizes.insert(FilesSizes.begin() + Idx, UnitSize); in RunOneMergeJob()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h629 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
634 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
H A DPPCISelLowering.cpp1997 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, in isVMerge() argument
2001 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && in isVMerge()
2004 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units in isVMerge()
2005 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit in isVMerge()
2006 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), in isVMerge()
2007 LHSStart+j+i*UnitSize) || in isVMerge()
2008 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), in isVMerge()
2009 RHSStart+j+i*UnitSize)) in isVMerge()
2021 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, in isVMRGLShuffleMask() argument
2025 return isVMerge(N, UnitSize, 0, 0); in isVMRGLShuffleMask()
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/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DDWARFYAML.cpp206 IO.mapRequired("UnitSize", Section.UnitSize); in mapping()
H A DDWARFEmitter.cpp232 writeInteger((uint32_t)Sect.UnitSize, OS, IsLittleEndian); in emitPubSection()
/freebsd/contrib/llvm-project/llvm/include/llvm/ObjectYAML/
H A DDWARFYAML.h89 uint32_t UnitSize; member
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp11477 unsigned UnitSize = 0; in EmitStructByval() local
11486 UnitSize = 1; in EmitStructByval()
11488 UnitSize = 2; in EmitStructByval()
11494 UnitSize = 16; in EmitStructByval()
11496 UnitSize = 8; in EmitStructByval()
11499 if (UnitSize == 0) in EmitStructByval()
11500 UnitSize = 4; in EmitStructByval()
11504 bool IsNeon = UnitSize >= 8; in EmitStructByval()
11507 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass in EmitStructByval()
11508 : UnitSize == 8 ? &ARM::DPRRegClass in EmitStructByval()
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