Home
last modified time | relevance | path

Searched refs:UndefReg (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp53 std::vector<Register> UndefReg; member in __anon1f03f2b70111::RegSeqInfo
61 UndefReg.emplace_back(Chan); in RegSeqInfo()
160 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()
162 Remap.emplace_back(It.second, Untouched->UndefReg[CurrentUndexIdx++]); in tryMergeVector()
189 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()
227 RSI->UndefReg = UpdatedUndef; in RebuildVector()
289 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()
304 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
H A DSIOptimizeVGPRLiveRange.cpp508 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() local
515 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeLiveRange()
560 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() local
577 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeWaterfallLiveRange()
H A DSILowerI1Copies.cpp427 Register UndefReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in insertUndefLaneMask() local
429 UndefReg); in insertUndefLaneMask()
430 return UndefReg; in insertUndefLaneMask()
H A DAMDGPUInstructionSelector.cpp2370 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2371 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2375 .addReg(UndefReg) in selectG_SZA_EXT()
2453 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2456 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2460 .addReg(UndefReg) in selectG_SZA_EXT()
H A DSIISelLowering.cpp15078 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
15081 UndefReg, Src0, SDValue()); in PostISelFolding()
15095 Src0 = UndefReg; in PostISelFolding()
15096 Src1 = UndefReg; in PostISelFolding()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp534 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
536 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()
538 .addReg(UndefReg) in adjustCallSequence()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp439 Register UndefReg = 0; in applyCombineShuffleConcat() local
443 if (UndefReg == 0) in applyCombineShuffleConcat()
444 UndefReg = Builder.buildUndef(SrcTy).getReg(0); in applyCombineShuffleConcat()
445 Reg = UndefReg; in applyCombineShuffleConcat()
524 Register UndefReg; in matchCombineShuffleVector() local
528 if (!UndefReg) { in matchCombineShuffleVector()
530 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
532 Ops.push_back(UndefReg); in matchCombineShuffleVector()
3080 Register UndefReg; in applyCombineInsertVecElts() local
3082 if (UndefReg) in applyCombineInsertVecElts()
[all …]
H A DLegalizerHelper.cpp1937 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
1939 Unmerges.push_back(UndefReg); in widenScalarMergeValues()