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Searched refs:UndefReg (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp53 std::vector<Register> UndefReg; member in __anon1f03f2b70111::RegSeqInfo
61 UndefReg.emplace_back(Chan); in RegSeqInfo()
159 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()
161 Remap.emplace_back(It.second, Untouched->UndefReg[CurrentUndexIdx++]); in tryMergeVector()
188 std::vector<Register> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()
226 RSI->UndefReg = UpdatedUndef; in RebuildVector()
289 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()
304 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
H A DSIOptimizeVGPRLiveRange.cpp513 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() local
520 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeLiveRange()
565 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() local
582 PHI.addReg(UndefReg, RegState::Undef).addMBB(Pred); in optimizeWaterfallLiveRange()
H A DSILowerI1Copies.cpp384 Register UndefReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in insertUndefLaneMask() local
386 UndefReg); in insertUndefLaneMask()
387 return UndefReg; in insertUndefLaneMask()
H A DAMDGPUInstructionSelector.cpp2614 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2615 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2619 .addReg(UndefReg) in selectG_SZA_EXT()
2697 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
2700 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg); in selectG_SZA_EXT()
2704 .addReg(UndefReg) in selectG_SZA_EXT()
H A DSIISelLowering.cpp16122 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
16124 SDValue ImpDef = DAG.getCopyToReg(DAG.getEntryNode(), SDLoc(Node), UndefReg, in PostISelFolding()
16139 Src0 = UndefReg; in PostISelFolding()
16140 Src1 = UndefReg; in PostISelFolding()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallFrameOptimization.cpp532 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
534 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()
536 .addReg(UndefReg) in adjustCallSequence()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp505 Register UndefReg = 0; in applyCombineShuffleConcat() local
509 if (UndefReg == 0) in applyCombineShuffleConcat()
510 UndefReg = Builder.buildUndef(SrcTy).getReg(0); in applyCombineShuffleConcat()
511 Reg = UndefReg; in applyCombineShuffleConcat()
590 Register UndefReg; in matchCombineShuffleVector() local
594 if (!UndefReg) { in matchCombineShuffleVector()
596 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
598 Ops.push_back(UndefReg); in matchCombineShuffleVector()
3115 Register UndefReg; in applyCombineInsertVecElts() local
3117 if (UndefReg) in applyCombineInsertVecElts()
[all …]
H A DLegalizerHelper.cpp2235 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
2237 Unmerges.push_back(UndefReg); in widenScalarMergeValues()