| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 42 UXTW,
62 case AArch64_AM::UXTW: return "uxtw"; in getShiftExtendName()
129 case 2: return AArch64_AM::UXTW; in getExtendType()
156 case AArch64_AM::UXTW: return 2; break; in getExtendEncoding()
43 UXTW, global() enumerator
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| H A D | AArch64InstPrinter.cpp | 1280 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at in printArithExtend()
1282 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1288 ExtType == AArch64_AM::UXTW) ) { in printMemExtendImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 20 def CheckExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
42 def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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| H A D | AArch64RegisterInfo.td | 1547 // UXTW(8|16|32|64)
1548 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1549 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
1550 def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
1551 def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
1552 def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
1554 …def ZPR#RegWidth#ExtUXTW8Only : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8, "On…
1555 def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
1556 def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
1557 def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
[all …]
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| H A D | AArch64FastISel.cpp | 757 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
781 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
839 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
876 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
896 Addr.setExtendType(AArch64_AM::UXTW); in computeAddress()
1079 Addr.getExtendType() == AArch64_AM::UXTW ) in simplifyAddress()
1088 if (Addr.getExtendType() == AArch64_AM::UXTW) in simplifyAddress()
1824 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitLoad()
2114 if (Addr.getExtendType() == AArch64_AM::UXTW || in emitStore()
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| H A D | AArch64ISelDAGToDAG.cpp | 831 return AArch64_AM::UXTW; in getExtendTypeForNode()
849 return AArch64_AM::UXTW; in getExtendTypeForNode()
972 if (Ext == AArch64_AM::UXTW && Reg->getValueType(0).getSizeInBits() == 32 && in SelectArithExtendedRegister()
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| H A D | AArch64InstrInfo.cpp | 958 case AArch64_AM::UXTW: in isFalkorShiftExtFast()
992 case AArch64_AM::UXTW: in isFalkorShiftExtFast()
3053 if (Extend != AArch64_AM::UXTW && Extend != AArch64_AM::SXTW) in canFoldIntoAddrMode()
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| H A D | AArch64InstrFormats.td | 2973 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
2975 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
3080 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 613 UXTW, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1347 if (!MatchShift && (ShiftExtendTy == AArch64_AM::UXTW || in isSVEDataVectorRegWithShiftExtend()
1539 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1552 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW; in isExtend64()
1584 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
2182 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
3598 .Case("uxtw", AArch64_AM::UXTW) in tryParseOptionalShiftExtend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 7618 return AArch64_AM::UXTW; in getExtendTypeForInst()
7641 return AArch64_AM::UXTW; in getExtendTypeForInst()
7710 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrMVE.td | 210 // mve_addr_rq_shift := reg + vreg{ << UXTW #shift}
6337 // [Rn,Qm,UXTW #2] or similar.
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