Home
last modified time | relevance | path

Searched refs:UTMIPLL_HW_PWRDN_CFG0 (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c1112 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg); in config_utmi_pll()
1116 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1126 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg); in config_utmi_pll()
1129 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1133 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg); in config_utmi_pll()
1135 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
H A Dtegra124_car.h267 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c1408 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg); in config_utmi_pll()
1410 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1450 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg); in config_utmi_pll()
1453 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1462 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg); in config_utmi_pll()
1464 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
H A Dtegra210_car.h373 #define UTMIPLL_HW_PWRDN_CFG0 0x52c macro