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Searched refs:USUBSAT (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h357 USUBSAT, enumerator
H A DTargetLowering.h2939 case ISD::USUBSAT: in isBinOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3607 { ISD::USUBSAT, MVT::v32i16, { 1 } }, in getIntrinsicInstrCost()
3608 { ISD::USUBSAT, MVT::v64i8, { 1 } }, in getIntrinsicInstrCost()
3681 { ISD::USUBSAT, MVT::v16i32, { 2 } }, // pmaxud + psubd in getIntrinsicInstrCost()
3682 { ISD::USUBSAT, MVT::v2i64, { 2 } }, // pmaxuq + psubq in getIntrinsicInstrCost()
3683 { ISD::USUBSAT, MVT::v4i64, { 2 } }, // pmaxuq + psubq in getIntrinsicInstrCost()
3684 { ISD::USUBSAT, MVT::v8i64, { 2 } }, // pmaxuq + psubq in getIntrinsicInstrCost()
3695 { ISD::USUBSAT, MVT::v32i16, { 2 } }, in getIntrinsicInstrCost()
3696 { ISD::USUBSAT, MVT::v64i8, { 2 } }, in getIntrinsicInstrCost()
3827 { ISD::USUBSAT, MVT::v16i16, { 1 } }, in getIntrinsicInstrCost()
3828 { ISD::USUBSAT, MVT::v32i8, { 1 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1135 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal); in X86TargetLowering()
1139 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal); in X86TargetLowering()
1141 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom); in X86TargetLowering()
1142 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom); in X86TargetLowering()
1587 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1591 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1594 setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom); in X86TargetLowering()
1596 setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom); in X86TargetLowering()
1964 setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
23241 SDValue Result = DAG.getNode(ISD::USUBSAT, dl, VT, Op0, Op1); in LowerVSETCCWithSUBUS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp360 case ISD::USUBSAT: return "usubsat"; in getOperationName()
H A DLegalizeVectorOps.cpp452 case ISD::USUBSAT: in LegalizeOp()
1040 case ISD::USUBSAT: in Expand()
H A DTargetLowering.cpp9275 if (!IsSigned && isOperationLegal(ISD::USUBSAT, VT)) in expandABD()
9277 DAG.getNode(ISD::USUBSAT, dl, VT, LHS, RHS), in expandABD()
9278 DAG.getNode(ISD::USUBSAT, dl, VT, RHS, LHS)); in expandABD()
10126 unsigned SubOpcode = NumSubElts <= NElts ? ISD::SUB : ISD::USUBSAT; in clampDynamicVectorIndex()
10264 isOperationLegal(ISD::USUBSAT, VT)) { in expandIntMINMAX()
10266 DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); in expandIntMINMAX()
10272 isOperationLegal(ISD::USUBSAT, VT)) { in expandIntMINMAX()
10274 DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); in expandIntMINMAX()
10336 if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { in expandAddSubSat()
10359 case ISD::USUBSAT: in expandAddSubSat()
[all …]
H A DLegalizeIntegerTypes.cpp231 case ISD::USUBSAT: in PromoteIntegerResult()
1056 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT()
1075 if (Opcode == ISD::USUBSAT) in PromoteIntRes_ADDSUBSHLSAT()
1076 return matcher.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted, in PromoteIntRes_ADDSUBSHLSAT()
2904 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; in ExpandIntegerResult()
H A DSelectionDAG.cpp4067 case ISD::USUBSAT: { in computeKnownBits()
5260 case ISD::USUBSAT: in canCreateUndefOrPoison()
6273 case ISD::USUBSAT: return C1.usub_sat(C2); in FoldValue()
6980 case ISD::USUBSAT: in getNode()
6989 if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT) in getNode()
7345 case ISD::USUBSAT: in getNode()
7370 case ISD::USUBSAT: in getNode()
12685 SDValue Hi = getNode(ISD::USUBSAT, DL, VT, N, HalfNumElts); in SplitEVL()
H A DDAGCombiner.cpp1844 case ISD::USUBSAT: return visitSUBSAT(N); in visit()
2802 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2809 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), in visitADDLike()
3717 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3733 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3740 !(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT))) in foldSubToUSubSat()
6852 return DAG.getNode(ISD::USUBSAT, DL, VT, X, in foldAndToUsubsat()
7342 if (hasOperation(ISD::USUBSAT, VT)) in visitAND()
12475 if (hasOperation(ISD::USUBSAT, VT)) { in visitVSELECT()
12512 return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
[all …]
H A DLegalizeVectorTypes.cpp162 case ISD::USUBSAT: in ScalarizeVectorResult()
1277 case ISD::USUBSAT: case ISD::VP_USUBSAT: in SplitVectorResult()
4397 case ISD::USUBSAT: case ISD::VP_USUBSAT: in WidenVectorResult()
H A DLegalizeDAG.cpp1153 case ISD::USUBSAT: in LegalizeOp()
3893 case ISD::USUBSAT: in ExpandNode()
H A DSelectionDAGBuilder.cpp7198 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def327 VP_PROPERTY_FUNCTIONAL_SDOPC(USUBSAT)
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp721 ISD::SSUBSAT, ISD::USUBSAT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp224 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
285 setOperationAction(ISD::USUBSAT, VT, Legal); in addMVEVectorTypes()
1155 setOperationAction(ISD::USUBSAT, MVT::i8, Custom); in ARMTargetLowering()
1157 setOperationAction(ISD::USUBSAT, MVT::i16, Custom); in ARMTargetLowering()
5099 case ISD::USUBSAT: in LowerADDSUBSAT()
5115 case ISD::USUBSAT: in LowerADDSUBSAT()
7885 case ISD::USUBSAT: in IsQRMVEInstruction()
10652 case ISD::USUBSAT: in LowerOperation()
10757 case ISD::USUBSAT: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp286 setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT}, in RISCVTargetLowering()
294 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Custom); in RISCVTargetLowering()
851 ISD::SSUBSAT, ISD::USUBSAT}, in RISCVTargetLowering()
1250 ISD::SSUBSAT, ISD::USUBSAT}, in RISCVTargetLowering()
5978 OP_CASE(USUBSAT) in getRISCVVLOp()
6025 VP_CASE(USUBSAT) // VP_USUBSAT in getRISCVVLOp()
7037 case ISD::USUBSAT: in LowerOperation()
12537 case ISD::USUBSAT: { in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp513 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Legal); in SITargetLowering()
553 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering()
776 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
795 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
5859 case ISD::USUBSAT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td455 def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp543 ISD::USUBSAT}, in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1278 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
1481 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
21433 return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
21445 return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp780 setOperationAction(ISD::USUBSAT, VT, Legal); in PPCTargetLowering()