1 /*-
2 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 #include <sys/stdint.h>
28 #include <sys/stddef.h>
29 #include <sys/param.h>
30 #include <sys/queue.h>
31 #include <sys/types.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/module.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38 #include <sys/condvar.h>
39 #include <sys/sysctl.h>
40 #include <sys/sx.h>
41 #include <sys/unistd.h>
42 #include <sys/callout.h>
43 #include <sys/malloc.h>
44 #include <sys/priv.h>
45
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <dev/usb/usb.h>
51 #include <dev/usb/usbdi.h>
52
53 #include <dev/usb/usb_core.h>
54 #include <dev/usb/usb_busdma.h>
55 #include <dev/usb/usb_process.h>
56 #include <dev/usb/usb_util.h>
57
58 #define USB_DEBUG_VAR usbssdebug
59
60 #include <dev/usb/usb_controller.h>
61 #include <dev/usb/usb_bus.h>
62 #include <dev/usb/controller/musb_otg.h>
63 #include <dev/usb/usb_debug.h>
64
65 #include <sys/rman.h>
66
67 #include <arm/ti/am335x/am335x_scm.h>
68 #include <arm/ti/ti_sysc.h>
69 #include <dev/clk/clk.h>
70 #include <dev/syscon/syscon.h>
71 #include "syscon_if.h"
72
73 #define USBCTRL_REV 0x00
74 #define USBCTRL_CTRL 0x14
75 #define USBCTRL_STAT 0x18
76 #define USBCTRL_IRQ_STAT0 0x30
77 #define IRQ_STAT0_RXSHIFT 16
78 #define IRQ_STAT0_TXSHIFT 0
79 #define USBCTRL_IRQ_STAT1 0x34
80 #define IRQ_STAT1_DRVVBUS (1 << 8)
81 #define USBCTRL_INTEN_SET0 0x38
82 #define USBCTRL_INTEN_SET1 0x3C
83 #define USBCTRL_INTEN_USB_ALL 0x1ff
84 #define USBCTRL_INTEN_USB_SOF (1 << 3)
85 #define USBCTRL_INTEN_CLR0 0x40
86 #define USBCTRL_INTEN_CLR1 0x44
87 #define USBCTRL_UTMI 0xE0
88 #define USBCTRL_UTMI_FSDATAEXT (1 << 1)
89 #define USBCTRL_MODE 0xE8
90 #define USBCTRL_MODE_IDDIG (1 << 8)
91 #define USBCTRL_MODE_IDDIGMUX (1 << 7)
92
93 /* USBSS resource + 2 MUSB ports */
94
95 #define RES_USBCORE 0
96 #define RES_USBCTRL 1
97
98 #define USB_WRITE4(sc, idx, reg, val) do { \
99 bus_write_4((sc)->sc_mem_res[idx], (reg), (val)); \
100 } while (0)
101
102 #define USB_READ4(sc, idx, reg) bus_read_4((sc)->sc_mem_res[idx], (reg))
103
104 #define USBCTRL_WRITE4(sc, reg, val) \
105 USB_WRITE4((sc), RES_USBCTRL, (reg), (val))
106 #define USBCTRL_READ4(sc, reg) \
107 USB_READ4((sc), RES_USBCTRL, (reg))
108
109 static struct resource_spec am335x_musbotg_mem_spec[] = {
110 { SYS_RES_MEMORY, 0, RF_ACTIVE },
111 { SYS_RES_MEMORY, 1, RF_ACTIVE },
112 { -1, 0, 0 }
113 };
114
115 #ifdef USB_DEBUG
116 static int usbssdebug = 0;
117
118 static SYSCTL_NODE(_hw_usb, OID_AUTO, am335x_usbss,
119 CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
120 "AM335x USBSS");
121 SYSCTL_INT(_hw_usb_am335x_usbss, OID_AUTO, debug, CTLFLAG_RW,
122 &usbssdebug, 0, "Debug level");
123 #endif
124
125 static device_probe_t musbotg_probe;
126 static device_attach_t musbotg_attach;
127 static device_detach_t musbotg_detach;
128
129 struct musbotg_super_softc {
130 struct musbotg_softc sc_otg;
131 struct resource *sc_mem_res[2];
132 int sc_irq_rid;
133 struct syscon *syscon;
134 };
135
136 static void
musbotg_vbus_poll(struct musbotg_super_softc * sc)137 musbotg_vbus_poll(struct musbotg_super_softc *sc)
138 {
139 uint32_t stat;
140
141 if (sc->sc_otg.sc_mode == MUSB2_DEVICE_MODE)
142 musbotg_vbus_interrupt(&sc->sc_otg, 1);
143 else {
144 stat = USBCTRL_READ4(sc, USBCTRL_STAT);
145 musbotg_vbus_interrupt(&sc->sc_otg, stat & 1);
146 }
147 }
148
149 /*
150 * Arg to musbotg_clocks_on and musbot_clocks_off is
151 * a uint32_t * pointing to the SCM register offset.
152 */
153 static uint32_t USB_CTRL[] = {SCM_USB_CTRL0, SCM_USB_CTRL1};
154
155 static void
musbotg_clocks_on(void * arg)156 musbotg_clocks_on(void *arg)
157 {
158 struct musbotg_softc *sc;
159 struct musbotg_super_softc *ssc;
160 uint32_t reg;
161
162 sc = arg;
163 ssc = sc->sc_platform_data;
164
165 reg = SYSCON_READ_4(ssc->syscon, USB_CTRL[sc->sc_id]);
166 reg &= ~3; /* Enable power */
167 reg |= 1 << 19; /* VBUS detect enable */
168 reg |= 1 << 20; /* Session end enable */
169
170 SYSCON_WRITE_4(ssc->syscon, USB_CTRL[sc->sc_id], reg);
171 }
172
173 static void
musbotg_clocks_off(void * arg)174 musbotg_clocks_off(void *arg)
175 {
176 struct musbotg_softc *sc;
177 struct musbotg_super_softc *ssc;
178 uint32_t reg;
179
180 sc = arg;
181 ssc = sc->sc_platform_data;
182
183 /* Disable power to PHY */
184 reg = SYSCON_READ_4(ssc->syscon, USB_CTRL[sc->sc_id]);
185 SYSCON_WRITE_4(ssc->syscon, USB_CTRL[sc->sc_id], reg | 3);
186 }
187
188 static void
musbotg_ep_int_set(struct musbotg_softc * sc,int ep,int on)189 musbotg_ep_int_set(struct musbotg_softc *sc, int ep, int on)
190 {
191 struct musbotg_super_softc *ssc = sc->sc_platform_data;
192 uint32_t epmask;
193
194 epmask = ((1 << ep) << IRQ_STAT0_RXSHIFT);
195 epmask |= ((1 << ep) << IRQ_STAT0_TXSHIFT);
196 if (on)
197 USBCTRL_WRITE4(ssc, USBCTRL_INTEN_SET0, epmask);
198 else
199 USBCTRL_WRITE4(ssc, USBCTRL_INTEN_CLR0, epmask);
200 }
201
202 static void
musbotg_wrapper_interrupt(void * arg)203 musbotg_wrapper_interrupt(void *arg)
204 {
205 struct musbotg_softc *sc = arg;
206 struct musbotg_super_softc *ssc = sc->sc_platform_data;
207 uint32_t stat, stat0, stat1;
208
209 stat = USBCTRL_READ4(ssc, USBCTRL_STAT);
210 stat0 = USBCTRL_READ4(ssc, USBCTRL_IRQ_STAT0);
211 stat1 = USBCTRL_READ4(ssc, USBCTRL_IRQ_STAT1);
212 if (stat0)
213 USBCTRL_WRITE4(ssc, USBCTRL_IRQ_STAT0, stat0);
214 if (stat1)
215 USBCTRL_WRITE4(ssc, USBCTRL_IRQ_STAT1, stat1);
216
217 DPRINTFN(4, "port%d: stat0=%08x stat1=%08x, stat=%08x\n",
218 sc->sc_id, stat0, stat1, stat);
219
220 if (stat1 & IRQ_STAT1_DRVVBUS)
221 musbotg_vbus_interrupt(sc, stat & 1);
222
223 musbotg_interrupt(arg, ((stat0 >> 16) & 0xffff),
224 stat0 & 0xffff, stat1 & 0xff);
225 }
226
227 static int
musbotg_probe(device_t dev)228 musbotg_probe(device_t dev)
229 {
230 if (!ofw_bus_status_okay(dev))
231 return (ENXIO);
232
233 if (!ofw_bus_is_compatible(dev, "ti,musb-am33xx"))
234 return (ENXIO);
235
236 device_set_desc(dev, "TI AM33xx integrated USB OTG controller");
237
238 return (BUS_PROBE_DEFAULT);
239 }
240
241 static int
musbotg_attach(device_t dev)242 musbotg_attach(device_t dev)
243 {
244 struct musbotg_super_softc *sc = device_get_softc(dev);
245 char mode[16];
246 int err;
247 uint32_t reg;
248 phandle_t opp_table;
249 clk_t clk_usbotg_fck;
250
251 sc->sc_otg.sc_id = device_get_unit(dev);
252
253 /* FIXME: The devicetree needs to be updated to get a handle to the gate
254 * usbotg_fck@47c. see TRM 8.1.12.2 CM_WKUP CM_CLKDCOLDO_DPLL_PER.
255 */
256 err = clk_get_by_name(dev, "usbotg_fck@47c", &clk_usbotg_fck);
257 if (err) {
258 device_printf(dev, "Can not find usbotg_fck@47c\n");
259 return (ENXIO);
260 }
261
262 err = clk_enable(clk_usbotg_fck);
263 if (err) {
264 device_printf(dev, "Can not enable usbotg_fck@47c\n");
265 return (ENXIO);
266 }
267
268 /* FIXME: For now; Go and kidnap syscon from opp-table */
269 opp_table = OF_finddevice("/opp-table");
270 if (opp_table == -1) {
271 device_printf(dev, "Cant find /opp-table\n");
272 return (ENXIO);
273 }
274 if (!OF_hasprop(opp_table, "syscon")) {
275 device_printf(dev, "/opp-table missing syscon property\n");
276 return (ENXIO);
277 }
278 err = syscon_get_by_ofw_property(dev, opp_table, "syscon", &sc->syscon);
279 if (err) {
280 device_printf(dev, "Failed to get syscon\n");
281 return (ENXIO);
282 }
283
284 /* Request the memory resources */
285 err = bus_alloc_resources(dev, am335x_musbotg_mem_spec,
286 sc->sc_mem_res);
287 if (err) {
288 device_printf(dev,
289 "Error: could not allocate mem resources\n");
290 return (ENXIO);
291 }
292
293 /* Request the IRQ resources */
294 sc->sc_otg.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
295 &sc->sc_irq_rid, RF_ACTIVE);
296 if (sc->sc_otg.sc_irq_res == NULL) {
297 device_printf(dev,
298 "Error: could not allocate irq resources\n");
299 return (ENXIO);
300 }
301
302 /* setup MUSB OTG USB controller interface softc */
303 sc->sc_otg.sc_clocks_on = &musbotg_clocks_on;
304 sc->sc_otg.sc_clocks_off = &musbotg_clocks_off;
305 sc->sc_otg.sc_clocks_arg = &sc->sc_otg;
306
307 sc->sc_otg.sc_ep_int_set = musbotg_ep_int_set;
308
309 /* initialise some bus fields */
310 sc->sc_otg.sc_bus.parent = dev;
311 sc->sc_otg.sc_bus.devices = sc->sc_otg.sc_devices;
312 sc->sc_otg.sc_bus.devices_max = MUSB2_MAX_DEVICES;
313 sc->sc_otg.sc_bus.dma_bits = 32;
314
315 /* get all DMA memory */
316 if (usb_bus_mem_alloc_all(&sc->sc_otg.sc_bus,
317 USB_GET_DMA_TAG(dev), NULL)) {
318 device_printf(dev,
319 "Failed allocate bus mem for musb\n");
320 return (ENOMEM);
321 }
322 sc->sc_otg.sc_io_res = sc->sc_mem_res[RES_USBCORE];
323 sc->sc_otg.sc_io_tag =
324 rman_get_bustag(sc->sc_otg.sc_io_res);
325 sc->sc_otg.sc_io_hdl =
326 rman_get_bushandle(sc->sc_otg.sc_io_res);
327 sc->sc_otg.sc_io_size =
328 rman_get_size(sc->sc_otg.sc_io_res);
329
330 sc->sc_otg.sc_bus.bdev = device_add_child(dev, "usbus", DEVICE_UNIT_ANY);
331 if (!(sc->sc_otg.sc_bus.bdev)) {
332 device_printf(dev, "No busdev for musb\n");
333 goto error;
334 }
335 device_set_ivars(sc->sc_otg.sc_bus.bdev,
336 &sc->sc_otg.sc_bus);
337
338 err = bus_setup_intr(dev, sc->sc_otg.sc_irq_res,
339 INTR_TYPE_BIO | INTR_MPSAFE,
340 NULL, (driver_intr_t *)musbotg_wrapper_interrupt,
341 &sc->sc_otg, &sc->sc_otg.sc_intr_hdl);
342 if (err) {
343 sc->sc_otg.sc_intr_hdl = NULL;
344 device_printf(dev,
345 "Failed to setup interrupt for musb\n");
346 goto error;
347 }
348
349 sc->sc_otg.sc_platform_data = sc;
350 if (OF_getprop(ofw_bus_get_node(dev), "dr_mode", mode,
351 sizeof(mode)) > 0) {
352 if (strcasecmp(mode, "host") == 0)
353 sc->sc_otg.sc_mode = MUSB2_HOST_MODE;
354 else
355 sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE;
356 } else {
357 /* Beaglebone defaults: USB0 device, USB1 HOST. */
358 if (sc->sc_otg.sc_id == 0)
359 sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE;
360 else
361 sc->sc_otg.sc_mode = MUSB2_HOST_MODE;
362 }
363
364 /*
365 * software-controlled function
366 */
367
368 if (sc->sc_otg.sc_mode == MUSB2_HOST_MODE) {
369 reg = USBCTRL_READ4(sc, USBCTRL_MODE);
370 reg |= USBCTRL_MODE_IDDIGMUX;
371 reg &= ~USBCTRL_MODE_IDDIG;
372 USBCTRL_WRITE4(sc, USBCTRL_MODE, reg);
373 USBCTRL_WRITE4(sc, USBCTRL_UTMI,
374 USBCTRL_UTMI_FSDATAEXT);
375 } else {
376 reg = USBCTRL_READ4(sc, USBCTRL_MODE);
377 reg |= USBCTRL_MODE_IDDIGMUX;
378 reg |= USBCTRL_MODE_IDDIG;
379 USBCTRL_WRITE4(sc, USBCTRL_MODE, reg);
380 }
381
382 reg = USBCTRL_INTEN_USB_ALL & ~USBCTRL_INTEN_USB_SOF;
383 USBCTRL_WRITE4(sc, USBCTRL_INTEN_SET1, reg);
384 USBCTRL_WRITE4(sc, USBCTRL_INTEN_CLR0, 0xffffffff);
385
386 err = musbotg_init(&sc->sc_otg);
387 if (!err)
388 err = device_probe_and_attach(sc->sc_otg.sc_bus.bdev);
389
390 if (err)
391 goto error;
392
393 /* poll VBUS one time */
394 musbotg_vbus_poll(sc);
395
396 return (0);
397
398 error:
399 musbotg_detach(dev);
400 return (ENXIO);
401 }
402
403 static int
musbotg_detach(device_t dev)404 musbotg_detach(device_t dev)
405 {
406 struct musbotg_super_softc *sc = device_get_softc(dev);
407 int error;
408
409 /* during module unload there are lots of children leftover */
410 error = bus_generic_detach(dev);
411 if (error != 0)
412 return (error);
413
414 if (sc->sc_otg.sc_irq_res && sc->sc_otg.sc_intr_hdl) {
415 /*
416 * only call musbotg_uninit() after musbotg_init()
417 */
418 musbotg_uninit(&sc->sc_otg);
419
420 bus_teardown_intr(dev, sc->sc_otg.sc_irq_res,
421 sc->sc_otg.sc_intr_hdl);
422 sc->sc_otg.sc_intr_hdl = NULL;
423 }
424
425 usb_bus_mem_free_all(&sc->sc_otg.sc_bus, NULL);
426
427 /* Free resources if any */
428 if (sc->sc_mem_res[0])
429 bus_release_resources(dev, am335x_musbotg_mem_spec,
430 sc->sc_mem_res);
431
432 if (sc->sc_otg.sc_irq_res)
433 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
434 sc->sc_otg.sc_irq_res);
435
436 return (0);
437 }
438
439 static device_method_t musbotg_methods[] = {
440 /* Device interface */
441 DEVMETHOD(device_probe, musbotg_probe),
442 DEVMETHOD(device_attach, musbotg_attach),
443 DEVMETHOD(device_detach, musbotg_detach),
444 DEVMETHOD(device_suspend, bus_generic_suspend),
445 DEVMETHOD(device_resume, bus_generic_resume),
446 DEVMETHOD(device_shutdown, bus_generic_shutdown),
447
448 DEVMETHOD_END
449 };
450
451 static driver_t musbotg_driver = {
452 .name = "musbotg",
453 .methods = musbotg_methods,
454 .size = sizeof(struct musbotg_super_softc),
455 };
456
457 DRIVER_MODULE(musbotg, ti_sysc, musbotg_driver, 0, 0);
458 MODULE_DEPEND(musbotg, ti_sysc, 1, 1, 1);
459 MODULE_DEPEND(musbotg, ti_am3359_cppi41, 1, 1, 1);
460 MODULE_DEPEND(usbss, usb, 1, 1, 1);
461