Searched refs:USAT (Results 1 – 11 of 11) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 1588 unsigned NarOpc = Signed ? HexagonISD::SSAT : HexagonISD::USAT; in resizeToWidth() 2948 case HexagonISD::USAT: in SplitVectorOp() 3262 case HexagonISD::USAT: in ExpandHvxResizeIntoSteps() 3297 case HexagonISD::USAT: in ExpandHvxResizeIntoSteps() 3413 case HexagonISD::USAT: in LowerHvxOperationWrapper() 3471 case HexagonISD::USAT: in ReplaceHvxNodeResults()
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H A D | HexagonISelLowering.h | 63 USAT, // Unsigned saturate. enumerator
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H A D | HexagonISelLowering.cpp | 1935 case HexagonISD::USAT: return "HexagonISD::USAT"; in getTargetNodeName() 3423 case HexagonISD::USAT: in LowerOperationWrapper()
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H A D | HexagonPatterns.td | 105 def HexagonUSAT: SDNode<"HexagonISD::USAT", SDTSaturate>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 100 USAT, // Unsigned saturation enumerator
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H A D | ARMInstrInfo.td | 166 def ARMusat : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 4113 def USAT : AI<(outs GPRnopc:$Rd), 4147 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 4151 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 4161 (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>; 4163 (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>; 4169 (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>; 4171 (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>; 6274 // SSAT/USAT optional shift operand. 6278 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
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H A D | ARMScheduleA57.td | 336 // Saturate: SSAT, SSAT16, USAT, USAT16 338 (instregex "(t2)?SSAT(16)?", "(t2)?USAT(16)?")>;
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H A D | ARMScheduleR52.td | 233 (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT",
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H A D | ARMScheduleSwift.td | 192 (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT",
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H A D | ARMISelLowering.cpp | 1730 MAKE_CASE(ARMISD::USAT) in getTargetNodeName() 5370 return DAG.getNode(ARMISD::USAT, dl, VT, V2Tmp, in LowerSaturatingConditional() 17966 return DAG.getNode(ARMISD::USAT, DL, VT, Input, in PerformMinMaxToSatCombine()
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H A D | ARMInstrThumb2.td | 5221 // SSAT/USAT optional shift operand.
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