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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h2418 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2421 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2555 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2558 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2728 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2731 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
3179 Ld->getAddressingMode() == ISD::UNINDEXED;
3209 return Ld && Ld->getAddressingMode() == ISD::UNINDEXED;
3217 St->getAddressingMode() == ISD::UNINDEXED;
3223 return St && St->getAddressingMode() == ISD::UNINDEXED;
H A DISDOpcodes.h1523 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
H A DBasicTTIImpl.h196 return ISD::UNINDEXED; in getISDIndexedMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp8920 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
8955 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
8962 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
8973 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo, in getExtLoad()
8981 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
9031 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO)); in getStore()
9040 ISD::UNINDEXED, false, VT, MMO); in getStore()
9098 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO)); in getTruncStore()
9107 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
9175 bool Indexed = AM != ISD::UNINDEXED; in getLoadVP()
[all …]
H A DLegalizeVectorTypes.cpp450 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
2050 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
2057 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI, in SplitVecRes_LOAD()
3069 EVL, MemVT, StoreMMO, ISD::UNINDEXED); in SplitVecRes_VP_REVERSE()
H A DSelectionDAGBuilder.cpp4808 VT, MMO, ISD::UNINDEXED, /*Truncating=*/false, in visitMaskedStore()
4995 ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding); in visitMaskedLoad()
8362 OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED, in visitVPStore()
8454 OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false, in visitVPStridedStore()
H A DTargetLowering.cpp9787 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
9937 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
H A DDAGCombiner.cpp18468 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
18765 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
18807 assert(AM != ISD::UNINDEXED); in SplitIndexingFromLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp3020 Thru.first, SingleTy, MOp0, ISD::UNINDEXED, in SplitHvxMemOp()
3024 Thru.second, SingleTy, MOp1, ISD::UNINDEXED, in SplitHvxMemOp()
3035 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
3038 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
3073 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in WidenHvxLoad()
3109 MemOp, ISD::UNINDEXED, false, false); in WidenHvxStore()
H A DHexagonISelDAGToDAG.cpp461 if (AM != ISD::UNINDEXED) { in SelectLoad()
570 if (AM != ISD::UNINDEXED) { in SelectStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1598 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1704 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()
1763 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
1779 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
H A DARMISelLowering.cpp17850 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, in PerformSplittingToWideningLoad()
18761 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, in PerformSplittingMVEEXTToWideningLoad()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td936 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
937 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1512 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
H A DSIISelLowering.cpp10202 ISD::UNINDEXED, ISD::NON_EXTLOAD, MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp756 if (AM == ISD::UNINDEXED) in tryIndexedLoad()
H A DRISCVISelLowering.cpp17123 ISD::UNINDEXED, ISD::NON_EXTLOAD); in PerformDAGCombine()
17192 ISD::UNINDEXED, false); in PerformDAGCombine()
17565 ISD::UNINDEXED, ISD::NON_EXTLOAD); in PerformDAGCombine()
17583 ISD::UNINDEXED, false); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp845 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()
H A DX86ISelLowering.cpp27258 MemVT, MemIntr->getMemOperand(), ISD::UNINDEXED, in LowerINTRINSIC_W_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp21722 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in performLDNT1Combine()
21794 ISD::UNINDEXED, false, false); in performSTNT1Combine()