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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h2533 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2536 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2667 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2670 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2840 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2843 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
3289 Ld->getAddressingMode() == ISD::UNINDEXED;
3319 return Ld && Ld->getAddressingMode() == ISD::UNINDEXED;
3327 St->getAddressingMode() == ISD::UNINDEXED;
3333 return St && St->getAddressingMode() == ISD::UNINDEXED;
H A DISDOpcodes.h1634 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
H A DBasicTTIImpl.h198 return ISD::UNINDEXED; in getISDIndexedMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9504 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
9540 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
9547 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
9558 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo, in getExtLoad()
9566 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
9608 ISD::UNINDEXED); in getStore()
9632 bool Indexed = AM != ISD::UNINDEXED; in getStore()
9684 return getStore(Chain, dl, Val, Ptr, Undef, SVT, MMO, ISD::UNINDEXED, true); in getTruncStore()
9726 bool Indexed = AM != ISD::UNINDEXED; in getLoadVP()
9764 return getLoadVP(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoadVP()
[all …]
H A DLegalizeVectorTypes.cpp462 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
2129 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
2136 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI, in SplitVecRes_LOAD()
3208 EVL, MemVT, StoreMMO, ISD::UNINDEXED); in SplitVecRes_VP_REVERSE()
3253 V1.getValueType(), StoreMMO, ISD::UNINDEXED); in SplitVecRes_VP_SPLICE()
3257 EVL2, V2.getValueType(), StoreMMO, ISD::UNINDEXED); in SplitVecRes_VP_SPLICE()
H A DSelectionDAGBuilder.cpp4882 VT, MMO, ISD::UNINDEXED, /*Truncating=*/false, in visitMaskedStore()
5069 ISD::UNINDEXED, ISD::NON_EXTLOAD, IsExpanding); in visitMaskedLoad()
8516 OpValues[2], OpValues[3], VT, MMO, ISD::UNINDEXED, in visitVPStore()
8608 OpValues[4], VT, MMO, ISD::UNINDEXED, /*IsTruncating*/ false, in visitVPStridedStore()
H A DTargetLowering.cpp10279 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
10427 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
H A DDAGCombiner.cpp19470 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
19764 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
19806 assert(AM != ISD::UNINDEXED); in SplitIndexingFromLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp3057 Thru.first, SingleTy, MOp0, ISD::UNINDEXED, in SplitHvxMemOp()
3061 Thru.second, SingleTy, MOp1, ISD::UNINDEXED, in SplitHvxMemOp()
3072 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
3075 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
3110 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in WidenHvxLoad()
3146 MemOp, ISD::UNINDEXED, false, false); in WidenHvxStore()
H A DHexagonISelDAGToDAG.cpp462 if (AM != ISD::UNINDEXED) { in SelectLoad()
571 if (AM != ISD::UNINDEXED) { in SelectStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1589 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1695 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()
1754 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
1770 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
H A DARMISelLowering.cpp17928 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, in PerformSplittingToWideningLoad()
18832 DAG.getLoad(ISD::UNINDEXED, NewExtType, NewToVT, DL, Ch, NewPtr, Offset, in PerformSplittingMVEEXTToWideningLoad()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td995 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
996 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1515 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
H A DSIISelLowering.cpp10879 ISD::UNINDEXED, ISD::NON_EXTLOAD, MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp830 if (AM == ISD::UNINDEXED) in tryIndexedLoad()
H A DRISCVISelLowering.cpp20170 ISD::UNINDEXED, ISD::NON_EXTLOAD); in PerformDAGCombine()
20239 ISD::UNINDEXED, false); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp889 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()
H A DX86ISelLowering.cpp28207 MemVT, MemIntr->getMemOperand(), ISD::UNINDEXED, in LowerINTRINSIC_W_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp22737 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in performLDNT1Combine()
22809 ISD::UNINDEXED, false, false); in performSTNT1Combine()