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Searched refs:UNDEF_IRO (Results 1 – 4 of 4) sorted by relevance

/freebsd/sys/dev/bxe/
H A D57710_int_offsets.h64 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
65 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
66 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
67 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
83 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
99 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
100 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
101 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
102 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId)
103 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
[all …]
H A D57711_int_offsets.h64 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_HIGIG_HDR_LENGTH_OFFSET(portId)
65 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PAGE_BASE_OFFSET(vfId)
66 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_PROD_OFFSET(vfId)
67 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_SPQ_DATA_OFFSET(vfId)
83 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_TIME_SYNC_TEST_ADDRESS_OFFSET
99 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_ERROR_HANDLER_STATISTICS_RAM_OFFSET
100 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_LB_PHYSICAL_QUEUES_INFO_OFFSET
101 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_QUEUE_ZONE_OFFSET(queueId)
102 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VF_ZONE_OFFSET(vfId)
103 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_FIVE_TUPLE_SRC_EN_OFFSET
[all …]
H A D57712_int_offsets.h109 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_LINE_OFFSET
110 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_VFC_TEST_RESULT_OFFSET
129 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // XSTORM_KUKU_TIME_SYNC_FLG_OFFSET(funcId)
145 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RSS_KEY_OFFSET(portId)
151 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_LINE_OFFSET
152 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_VFC_TEST_RESULT_OFFSET
174 …{UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcInd…
217 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId)
236 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId)
237 {UNDEF_IRO, 0x0, 0x0, 0x0, 0x0}, // TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId)
[all …]
H A Decore_fw_defs.h422 #define UNDEF_IRO 0x80000000 macro