| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 339 UMULO, enumerator
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| H A D | SelectionDAGNodes.h | 3264 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 97 for (auto OP : {ISD::SMULO, ISD::UMULO}) { in M68kTargetLowering()
1387 case ISD::UMULO: in LowerOperation()
1542 case ISD::UMULO: in isOverflowArithmetic()
1594 case ISD::UMULO: in lowerOverflowArithmetic()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 348 case ISD::UMULO: return "umulo"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 218 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
1816 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
2898 case ISD::UMULO: in ExpandIntegerResult()
4263 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
4911 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
4939 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, LHSHigh, RHSLow); in ExpandIntRes_XMULO()
4942 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, RHSHigh, LHSLow); in ExpandIntRes_XMULO()
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| H A D | LegalizeVectorOps.cpp | 446 case ISD::UMULO: in LegalizeOp()
1036 case ISD::UMULO: in Expand()
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| H A D | LegalizeVectorTypes.cpp | 213 case ISD::UMULO: in ScalarizeVectorResult()
1312 case ISD::UMULO: in SplitVectorResult()
4469 case ISD::UMULO: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 3559 case ISD::UMULO: in computeKnownBits()
4717 case ISD::UMULO: in ComputeNumSignBits()
12482 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
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| H A D | TargetLowering.cpp | 10673 } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) { in expandFixedPointMul()
10675 DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()
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| H A D | LegalizeDAG.cpp | 3989 case ISD::UMULO: in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 7496 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 1877 case ISD::UMULO: return visitMULO(N); in visit()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1858 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
3163 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3290 case ISD::UMULO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 4116 { ISD::UMULO, MVT::i64, { 2 } }, // mulq + seto in getIntrinsicInstrCost()
4172 { ISD::UMULO, MVT::i32, { 2 } }, // mul + seto in getIntrinsicInstrCost()
4173 { ISD::UMULO, MVT::i16, { 2 } }, in getIntrinsicInstrCost()
4174 { ISD::UMULO, MVT::i8, { 2 } }, in getIntrinsicInstrCost()
4290 ISD = ISD::UMULO; in getIntrinsicInstrCost()
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| H A D | X86ISelLowering.cpp | 1117 setOperationAction(ISD::UMULO, MVT::v16i8, Custom); in X86TargetLowering()
1118 setOperationAction(ISD::UMULO, MVT::v2i32, Custom); in X86TargetLowering()
1577 setOperationAction(ISD::UMULO, MVT::v32i8, Custom); in X86TargetLowering()
1919 setOperationAction(ISD::UMULO, MVT::v64i8, Custom); in X86TargetLowering()
2438 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
23985 case ISD::UMULO: in getX86XALUOOp()
24265 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
32470 case ISD::UMULO: return LowerMULO(Op, Subtarget, DAG); in LowerOperation()
32606 case ISD::UMULO: { in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 733 ISD::SMULO, ISD::UMULO}, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 541 ISD::UMIN, ISD::UMULO, ISD::UMUL_LOHI, ISD::UREM, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 707 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
708 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
4004 case ISD::UMULO: { in getAArch64XALUOOp()
6809 case ISD::UMULO: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4967 case ISD::UMULO: in getARMXALUOOp()
5720 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()
5771 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 841 setOperationAction({ISD::SMULO, ISD::UMULO}, MVT::i64, Custom); in SITargetLowering()
5866 case ISD::UMULO: in LowerOperation()
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