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Searched refs:UINT_TO_FP (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2400 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2401 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, { 1, 1, 1, 1 } }, in getCastInstrCost()
2522 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, { 4, 1, 1, 1 } }, in getCastInstrCost()
2523 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, { 3, 1, 1, 1 } }, in getCastInstrCost()
2524 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, { 2, 1, 1, 1 } }, in getCastInstrCost()
2525 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, { 1, 1, 1, 1 } }, in getCastInstrCost()
2526 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, { 2, 1, 1, 1 } }, in getCastInstrCost()
2527 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, { 1, 1, 1, 1 } }, in getCastInstrCost()
2528 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, { 1, 1, 1, 1 } }, in getCastInstrCost()
2529 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, { 1, 1, 1, 1 } }, in getCastInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp706 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
709 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
711 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
713 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
715 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
717 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
719 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
721 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
723 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
725 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp191 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
196 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addTypeForNEON()
322 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
481 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
492 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
952 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
953 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1078 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
6080 case ISD::UINT_TO_FP: in LowerVectorINT_TO_FP()
6082 Opc = ISD::UINT_TO_FP; in LowerVectorINT_TO_FP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp3235 {ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1}, in getCastInstrCost()
3236 {ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1}, in getCastInstrCost()
3237 {ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1}, in getCastInstrCost()
3245 {ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i8, in getCastInstrCost()
3247 {ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i16, SVE_FCVT_COST}, in getCastInstrCost()
3248 {ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i32, SVE_FCVT_COST}, in getCastInstrCost()
3249 {ISD::UINT_TO_FP, MVT::nxv2f16, MVT::nxv2i64, SVE_FCVT_COST}, in getCastInstrCost()
3256 {ISD::UINT_TO_FP, MVT::nxv4f16, MVT::nxv4i8, in getCastInstrCost()
3258 {ISD::UINT_TO_FP, MVT::nxv4f16, MVT::nxv4i16, SVE_FCVT_COST}, in getCastInstrCost()
3259 {ISD::UINT_TO_FP, MVT::nxv4f16, MVT::nxv4i32, SVE_FCVT_COST}, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp596 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
597 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
598 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
1132 ISD::UINT_TO_FP}); in AArch64TargetLowering()
1257 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP, ISD::UINT_TO_FP, in AArch64TargetLowering()
1265 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32); in AArch64TargetLowering()
1271 for (auto Op : {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::STRICT_SINT_TO_FP, in AArch64TargetLowering()
1281 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); in AArch64TargetLowering()
1283 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom); in AArch64TargetLowering()
1285 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def59 DAG_INSTRUCTION(UIToFP, 1, 1, experimental_constrained_uitofp, UINT_TO_FP)
H A DVPIntrinsics.def481 HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, UINT_TO_FP)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h863 UINT_TO_FP, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp259 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
334 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
439 setOperationAction(ISD::UINT_TO_FP, VecTy, Custom); in initializeHVXLowering()
2340 Op.getOpcode() == ISD::UINT_TO_FP); in LowerHvxIntToFp()
2714 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2865 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
3192 case ISD::UINT_TO_FP: in LowerHvxOperation()
3274 case ISD::UINT_TO_FP: return LowerHvxIntToFp(Op, DAG); in LowerHvxOperation()
3441 case ISD::UINT_TO_FP: in LowerHvxOperationWrapper()
H A DHexagonISelLowering.cpp1873 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1874 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1875 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp498 case ISD::UINT_TO_FP: in LegalizeOp()
714 case ISD::UINT_TO_FP: in Promote()
834 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteINT_TO_FP()
1017 case ISD::UINT_TO_FP: in Expand()
1874 UIToFP = DAG.getNode(ISD::UINT_TO_FP, DL, FloatVecVT, Src); in ExpandUINT_TO_FLOAT()
H A DSelectionDAGDumper.cpp410 case ISD::UINT_TO_FP: return "uint_to_fp"; in getOperationName()
H A DLegalizeDAG.cpp1035 case ISD::UINT_TO_FP: in LegalizeOp()
2896 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP; in PromoteLegalINT_TO_FP()
3454 case ISD::UINT_TO_FP: in ExpandNode()
5017 case ISD::UINT_TO_FP: { in ConvertNodeToLibcall()
5290 if (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteNode()
5401 case ISD::UINT_TO_FP: in PromoteNode()
H A DLegalizeFloatTypes.cpp167 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; in SoftenFloatResult()
1635 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; in ExpandFloatResult()
2903 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; in PromoteFloatResult()
3386 case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break; in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp130 case ISD::UINT_TO_FP: in ScalarizeVectorResult()
760 case ISD::UINT_TO_FP: in ScalarizeVectorOperand()
1265 case ISD::UINT_TO_FP: in SplitVectorResult()
3454 case ISD::UINT_TO_FP: in SplitVectorOperand()
4879 case ISD::UINT_TO_FP: in WidenVectorResult()
6866 case ISD::UINT_TO_FP: in WidenVectorOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp205 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
297 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
2387 case ISD::UINT_TO_FP: in LowerConvertLow()
2918 assert(N->getOpcode() == ISD::UINT_TO_FP || in performVectorExtendToFPCombine()
2932 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in performVectorExtendToFPCombine()
3517 case ISD::UINT_TO_FP: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
231 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in XtensaTargetLowering()
238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp502 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
527 ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, in AMDGPUTargetLowering()
1458 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1985 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2127 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
2128 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
3361 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
3398 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
3401 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
3423 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
[all …]
H A DR600ISelLowering.cpp1730 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1731 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp286 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
287 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, RegVT); in PPCTargetLowering()
302 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
550 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
564 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
706 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
737 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
747 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
936 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
1128 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1685 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1687 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3119 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3484 case ISD::UINT_TO_FP: in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp237 for (auto Op : {ISD::UINT_TO_FP, ISD::STRICT_UINT_TO_FP}) { in SystemZTargetLowering()
296 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in SystemZTargetLowering()
507 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
508 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
527 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
528 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
793 ISD::UINT_TO_FP, in SystemZTargetLowering()
7148 case ISD::UINT_TO_FP: in LowerOperation()
7307 case ISD::UINT_TO_FP: in LowerOperationWrapper()
8536 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND); in combineINT_TO_FP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp214 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64 in initSPUActions()
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in initSPUActions()
2897 case ISD::UINT_TO_FP: in isI32Insn()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp651 ISD::UDIV, ISD::UDIVREM, ISD::UINT_TO_FP, ISD::UMAX, in NVPTXTargetLowering()
814 ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::SETCC}, in NVPTXTargetLowering()
925 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
929 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in NVPTXTargetLowering()
2922 case ISD::UINT_TO_FP: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp134 setOperationAction(ISD::UINT_TO_FP, GRLenVT, Expand); in LoongArchTargetLowering()
222 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in LoongArchTargetLowering()
318 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); in LoongArchTargetLowering()
385 setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal); in LoongArchTargetLowering()
486 case ISD::UINT_TO_FP: in LowerOperation()

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