/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 348 UADDSAT, enumerator
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H A D | TargetLowering.h | 2903 case ISD::UADDSAT: in isCommutativeBinOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 3601 { ISD::UADDSAT, MVT::v32i16, { 1 } }, in getIntrinsicInstrCost() 3602 { ISD::UADDSAT, MVT::v64i8, { 1 } }, in getIntrinsicInstrCost() 3685 { ISD::UADDSAT, MVT::v16i32, { 3 } }, // not + pminud + paddd in getIntrinsicInstrCost() 3686 { ISD::UADDSAT, MVT::v2i64, { 3 } }, // not + pminuq + paddq in getIntrinsicInstrCost() 3687 { ISD::UADDSAT, MVT::v4i64, { 3 } }, // not + pminuq + paddq in getIntrinsicInstrCost() 3688 { ISD::UADDSAT, MVT::v8i64, { 3 } }, // not + pminuq + paddq in getIntrinsicInstrCost() 3693 { ISD::UADDSAT, MVT::v32i16, { 2 } }, in getIntrinsicInstrCost() 3694 { ISD::UADDSAT, MVT::v64i8, { 2 } }, in getIntrinsicInstrCost() 3814 { ISD::UADDSAT, MVT::v16i16, { 1 } }, in getIntrinsicInstrCost() 3815 { ISD::UADDSAT, MVT::v32i8, { 1 } }, in getIntrinsicInstrCost() [all …]
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H A D | X86ISelLowering.cpp | 1133 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal); in X86TargetLowering() 1137 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal); in X86TargetLowering() 1356 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom); in X86TargetLowering() 1398 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom); in X86TargetLowering() 1585 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering() 1589 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering() 1593 setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom); in X86TargetLowering() 1595 setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom); in X86TargetLowering() 1962 setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering() 32479 case ISD::UADDSAT: in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 358 case ISD::UADDSAT: return "uaddsat"; in getOperationName()
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H A D | LegalizeVectorOps.cpp | 450 case ISD::UADDSAT: in LegalizeOp() 1042 case ISD::UADDSAT: in Expand()
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H A D | LegalizeIntegerTypes.cpp | 229 case ISD::UADDSAT: in PromoteIntegerResult() 1056 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT() 1066 if (Opcode == ISD::UADDSAT) { in PromoteIntRes_ADDSUBSHLSAT() 2902 case ISD::UADDSAT: in ExpandIntegerResult()
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H A D | SelectionDAG.cpp | 5258 case ISD::UADDSAT: in canCreateUndefOrPoison() 5555 case ISD::UADDSAT: in isKnownNeverZero() 6271 case ISD::UADDSAT: return C1.uadd_sat(C2); in FoldValue() 6979 case ISD::UADDSAT: in getNode() 6986 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode() 7374 case ISD::UADDSAT: in getNode()
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H A D | LegalizeVectorTypes.cpp | 156 case ISD::UADDSAT: in ScalarizeVectorResult() 1271 case ISD::UADDSAT: case ISD::VP_UADDSAT: in SplitVectorResult() 4391 case ISD::UADDSAT: case ISD::VP_UADDSAT: in WidenVectorResult()
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H A D | LegalizeDAG.cpp | 1151 case ISD::UADDSAT: in LegalizeOp() 3891 case ISD::UADDSAT: in ExpandNode()
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H A D | TargetLowering.cpp | 10342 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat() 10353 case ISD::UADDSAT: in expandAddSubSat() 10380 if (Opcode == ISD::UADDSAT) { in expandAddSubSat()
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H A D | SelectionDAGBuilder.cpp | 7184 setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall() 7947 ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); in visitIntrinsicCall()
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H A D | DAGCombiner.cpp | 1842 case ISD::UADDSAT: return visitADDSAT(N); in visit() 12428 if (hasOperation(ISD::UADDSAT, VT)) { in visitVSELECT() 12455 return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT() 12469 return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | VPIntrinsics.def | 315 VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 720 ISD::SADDSAT, ISD::UADDSAT, in initActions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 224 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON() 283 setOperationAction(ISD::UADDSAT, VT, Legal); in addMVEVectorTypes() 1154 setOperationAction(ISD::UADDSAT, MVT::i8, Custom); in ARMTargetLowering() 1156 setOperationAction(ISD::UADDSAT, MVT::i16, Custom); in ARMTargetLowering() 5093 case ISD::UADDSAT: in LowerADDSUBSAT() 5109 case ISD::UADDSAT: in LowerADDSUBSAT() 7881 case ISD::UADDSAT: in IsQRMVEInstruction() 10651 case ISD::UADDSAT: in LowerOperation() 10756 case ISD::UADDSAT: in ReplaceNodeResults()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 286 setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT}, in RISCVTargetLowering() 294 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Custom); in RISCVTargetLowering() 850 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering() 1249 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering() 5975 OP_CASE(UADDSAT) in getRISCVVLOp() 6022 VP_CASE(UADDSAT) // VP_UADDSAT in getRISCVVLOp() 7034 case ISD::UADDSAT: in LowerOperation() 12534 case ISD::UADDSAT: in ReplaceNodeResults()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 198 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 513 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Legal); in SITargetLowering() 553 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering() 776 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering() 795 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering() 5858 case ISD::UADDSAT: in LowerOperation()
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H A D | AMDGPUISelLowering.cpp | 3189 unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT; in LowerCTLZ_CTTZ()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 449 def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 535 ISD::SUBE, ISD::UADDO, ISD::UADDO_CARRY, ISD::UADDSAT, in NVPTXTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1276 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering() 1479 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering() 21428 return convertMergedOpToPredOp(N, ISD::UADDSAT, DAG, true); in performIntrinsicCombine() 21439 return DAG.getNode(ISD::UADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 779 setOperationAction(ISD::UADDSAT, VT, Legal); in PPCTargetLowering()
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