| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3759 { ISD::UADDSAT, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3760 { ISD::UADDSAT, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3863 { ISD::UADDSAT, MVT::v2i64, { 1, 4, 4, 4 } }, in getIntrinsicInstrCost()
3864 { ISD::UADDSAT, MVT::v4i64, { 1, 4, 4, 4 } }, in getIntrinsicInstrCost()
3865 { ISD::UADDSAT, MVT::v8i64, { 1, 4, 4, 4 } }, in getIntrinsicInstrCost()
3866 { ISD::UADDSAT, MVT::v4i32, { 1, 2, 4, 4 } }, in getIntrinsicInstrCost()
3867 { ISD::UADDSAT, MVT::v8i32, { 1, 2, 4, 4 } }, in getIntrinsicInstrCost()
3868 { ISD::UADDSAT, MVT::v16i32, { 2, 2, 4, 4 } }, in getIntrinsicInstrCost()
3869 { ISD::UADDSAT, MVT::v32i16, { 2, 2, 2, 2 } }, in getIntrinsicInstrCost()
3870 { ISD::UADDSAT, MVT::v64i8, { 2, 2, 2, 2 } }, in getIntrinsicInstrCost()
[all …]
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| H A D | X86ISelLowering.cpp | 1154 setOperationAction(ISD::UADDSAT, MVT::v16i8, Legal); in X86TargetLowering()
1158 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal); in X86TargetLowering()
1377 setOperationAction(ISD::UADDSAT, MVT::v4i32, Custom); in X86TargetLowering()
1419 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom); in X86TargetLowering()
1609 setOperationAction(ISD::UADDSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1613 setOperationAction(ISD::UADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1617 setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom); in X86TargetLowering()
1619 setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom); in X86TargetLowering()
1994 setOperationAction(ISD::UADDSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
33704 case ISD::UADDSAT: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 361 UADDSAT, enumerator
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| H A D | BasicTTIImpl.h | 2516 ISD = ISD::UADDSAT; in getTypeBasedIntrinsicInstrCost()
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| H A D | TargetLowering.h | 2987 case ISD::UADDSAT: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 375 case ISD::UADDSAT: return "uaddsat"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 467 case ISD::UADDSAT: in LegalizeOp()
1173 case ISD::UADDSAT: in Expand()
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| H A D | LegalizeIntegerTypes.cpp | 249 case ISD::UADDSAT: in PromoteIntegerResult()
1096 if (Opcode == ISD::UADDSAT) { in PromoteIntRes_ADDSUBSHLSAT()
1103 return matcher.getNode(ISD::UADDSAT, dl, NVT, Op1, Op2); in PromoteIntRes_ADDSUBSHLSAT()
3085 case ISD::UADDSAT: in ExpandIntegerResult()
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| H A D | SelectionDAG.cpp | 5542 case ISD::UADDSAT: in canCreateUndefOrPoison()
5952 case ISD::UADDSAT: in isKnownNeverZero()
6685 case ISD::UADDSAT: return C1.uadd_sat(C2); in FoldValue()
7524 case ISD::UADDSAT: in getNode()
7531 if (Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) in getNode()
7903 case ISD::UADDSAT: in getNode()
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| H A D | LegalizeVectorTypes.cpp | 171 case ISD::UADDSAT: in ScalarizeVectorResult()
1334 case ISD::UADDSAT: case ISD::VP_UADDSAT: in SplitVectorResult()
3328 SDValue HiStartVal = DAG.getNode(ISD::UADDSAT, DL, OpVT, Op0, LoElts); in SplitVecRes_GET_ACTIVE_LANE_MASK()
4763 case ISD::UADDSAT: case ISD::VP_UADDSAT: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 1181 case ISD::UADDSAT: in LegalizeOp()
4030 case ISD::UADDSAT: in ExpandNode()
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| H A D | TargetLowering.cpp | 10834 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat()
10845 case ISD::UADDSAT: in expandAddSubSat()
10872 if (Opcode == ISD::UADDSAT) { in expandAddSubSat()
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| H A D | SelectionDAGBuilder.cpp | 7238 setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
8052 ISD::UADDSAT, sdl, VecTy, VectorIndex, VectorStep); in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 1900 case ISD::UADDSAT: return visitADDSAT(N); in visit()
13290 if (hasOperation(ISD::UADDSAT, VT)) { in visitVSELECT()
13317 return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
13331 return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 288 VP_PROPERTY_FUNCTIONAL_SDOPC(UADDSAT)
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 801 ISD::SADDSAT, ISD::UADDSAT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 209 setOperationAction(ISD::UADDSAT, T, Legal); in initializeHVXLowering()
302 setOperationAction(ISD::UADDSAT, T, Legal); in initializeHVXLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 229 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
288 setOperationAction(ISD::UADDSAT, VT, Legal); in addMVEVectorTypes()
1156 setOperationAction(ISD::UADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1158 setOperationAction(ISD::UADDSAT, MVT::i16, Custom); in ARMTargetLowering()
5156 case ISD::UADDSAT: in LowerADDSUBSAT()
5172 case ISD::UADDSAT: in LowerADDSUBSAT()
7931 case ISD::UADDSAT: in IsQRMVEInstruction()
10712 case ISD::UADDSAT: in LowerOperation()
10819 case ISD::UADDSAT: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 339 {ISD::SADDSAT, ISD::SSUBSAT, ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, in RISCVTargetLowering()
444 setOperationAction(ISD::UADDSAT, MVT::i32, Legal); in RISCVTargetLowering()
898 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
1368 ISD::AVGCEILU, ISD::SADDSAT, ISD::UADDSAT, in RISCVTargetLowering()
6982 OP_CASE(UADDSAT) in getRISCVVLOp()
7029 VP_CASE(UADDSAT) // VP_UADDSAT in getRISCVVLOp()
8152 case ISD::UADDSAT: in LowerOperation()
14431 case ISD::UADDSAT: in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 528 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Legal); in SITargetLowering()
569 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering()
802 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
822 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
6203 case ISD::UADDSAT: in LowerOperation()
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| H A D | AMDGPUISelLowering.cpp | 3247 unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT; in LowerCTLZ_CTTZ()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 469 def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 216 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1328 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering()
1571 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering()
6021 return DAG.getNode(ISD::UADDSAT, DL, Op.getValueType(), Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
18256 Idx = DAG.getNode(ISD::UADDSAT, DL, OpVT, Idx, Elts); in performActiveLaneMaskCombine()
22292 return convertMergedOpToPredOp(N, ISD::UADDSAT, DAG, true); in performIntrinsicCombine()
22303 return DAG.getNode(ISD::UADDSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 650 ISD::SUBE, ISD::UADDO, ISD::UADDO_CARRY, ISD::UADDSAT, in NVPTXTargetLowering()
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