Searched refs:UACC (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfoMMA.td | 9 // Register info for registers related to MMA. These are the ACC and UACC
25 // UACC - One of the 8 512-bit VSX accumulators prior to being primed.
29 class UACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
64 def UACC0 : UACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>;
65 def UACC1 : UACC<1, "acc1", [VSRp2, VSRp3]>, DwarfRegNum<[-1, -1]>;
66 def UACC2 : UACC<2, "acc2", [VSRp4, VSRp5]>, DwarfRegNum<[-1, -1]>;
67 def UACC3 : UACC<3, "acc3", [VSRp6, VSRp7]>, DwarfRegNum<[-1, -1]>;
68 def UACC4 : UACC<4, "acc4", [VSRp8, VSRp9]>, DwarfRegNum<[-1, -1]>;
69 def UACC5 : UACC<5, "acc5", [VSRp10, VSRp11]>, DwarfRegNum<[-1, -1]>;
70 def UACC6 : UACC<6, "acc6", [VSRp12, VSRp13]>, DwarfRegNum<[-1, -1]>;
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| H A D | PPCInstrInfo.cpp | 3109 MCRegister UACC = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
3110 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) { in expandPostRAPseudo()
3111 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4; in expandPostRAPseudo()
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