Searched refs:TypeStoreSize (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUAsanInstrumentation.cpp | 81 uint32_t TypeStoreSize, int AsanScale) { in createSlowPathCmp() argument
87 if (TypeStoreSize / 8 > 1) in createSlowPathCmp()
89 LastAccessedByte, ConstantInt::get(IntptrTy, TypeStoreSize / 8 - 1)); in createSlowPathCmp()
153 Align Alignment, uint32_t TypeStoreSize, in instrumentAddressImpl() argument
161 size_t AccessSizeIndex = TypeStoreSizeToSizeIndex(TypeStoreSize); in instrumentAddressImpl()
163 std::max(8U, TypeStoreSize >> AsanScale)); in instrumentAddressImpl()
174 TypeStoreSize, AsanScale); in instrumentAddressImpl()
185 TypeSize TypeStoreSize, bool IsWrite, in instrumentAddress() argument
188 if (!TypeStoreSize.isScalable()) { in instrumentAddress()
190 const auto FixedSize = TypeStoreSize.getFixedValue(); in instrumentAddress()
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| H A D | AMDGPUAsanInstrumentation.h | 47 TypeSize TypeStoreSize, bool IsWrite,
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| H A D | AMDGPUSwLowerLDS.cpp | 1288 Operand.Alignment.valueOrOne(), Operand.TypeStoreSize, in run()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Instrumentation/ |
| H A D | AddressSanitizerCommon.h | 30 TypeSize TypeStoreSize = TypeSize::getFixed(0); variable
47 TypeStoreSize = DL.getTypeStoreSizeInBits(OpType); in IsWrite()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | AddressSanitizer.cpp | 815 uint32_t TypeStoreSize, bool IsWrite,
820 uint32_t TypeStoreSize, bool IsWrite,
826 TypeSize TypeStoreSize, bool IsWrite,
838 Value *ShadowValue, uint32_t TypeStoreSize);
859 TypeSize TypeStoreSize) const;
1661 TypeSize TypeStoreSize, bool IsWrite, in doInstrumentAddress() argument
1666 if (!TypeStoreSize.isScalable()) { in doInstrumentAddress()
1667 const auto FixedSize = TypeStoreSize.getFixedValue(); in doInstrumentAddress()
1681 Pass->instrumentUnusualSizeOrAlignment(I, InsertBefore, Addr, TypeStoreSize, in doInstrumentAddress()
1775 isSafeAccess(ObjSizeVis, Addr, O.TypeStoreSize)) { in instrumentMop()
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| H A D | HWAddressSanitizer.cpp | 1150 if (!O.TypeStoreSize.isScalable() && isPowerOf2_64(O.TypeStoreSize) && in instrumentMemAccess()
1151 (O.TypeStoreSize / 8 <= (1ULL << (kNumberOfAccessSizes - 1))) && in instrumentMemAccess()
1153 *O.Alignment >= O.TypeStoreSize / 8)) { in instrumentMemAccess()
1154 size_t AccessSizeIndex = TypeSizeToSizeIndex(O.TypeStoreSize); in instrumentMemAccess()
1171 IRB.CreateUDiv(IRB.CreateTypeSize(IntptrTy, O.TypeStoreSize), in instrumentMemAccess()
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