| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 732 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
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| H A D | SystemZISelLowering.cpp | 6633 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const { in combineTruncateExtract() argument
6638 TruncVT.getSizeInBits() % 8 == 0) { in combineTruncateExtract()
6644 unsigned TruncBytes = TruncVT.getStoreSize(); in combineTruncateExtract()
6659 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT); in combineTruncateExtract()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 6907 EVT TruncVT = TLI->getValueType(*DL, I->getType()); in optimizeLoadExt() local
6908 unsigned TruncBitWidth = TruncVT.getSizeInBits(); in optimizeLoadExt()
6936 EVT TruncVT = TLI->getValueType(*DL, TruncTy); in optimizeLoadExt() local
6939 if (!LoadResultVT.bitsGT(TruncVT) || !TruncVT.isRound() || in optimizeLoadExt()
6940 !TLI->isLoadExtLegal(ISD::ZEXTLOAD, LoadResultVT, TruncVT)) in optimizeLoadExt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1062 bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT,
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| H A D | X86ISelLowering.cpp | 10114 MVT TruncVT = MVT::getVectorVT(DstSVT, NumSrcElts); in getAVX512TruncNode() local
10115 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Src); in getAVX512TruncNode()
10120 MVT TruncVT = MVT::getVectorVT(DstSVT, NumSrcElts); in getAVX512TruncNode() local
10121 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, Src); in getAVX512TruncNode()
10134 MVT TruncVT = MVT::getVectorVT(DstSVT, 128 / DstEltSizeInBits); in getAVX512TruncNode() local
10135 SDValue Trunc = DAG.getNode(X86ISD::VTRUNC, DL, TruncVT, Src); in getAVX512TruncNode()
10136 if (DstVT != TruncVT) in getAVX512TruncNode()
20609 MVT TruncVT = MVT::getVectorVT(MVT::i32, NumElems); in LowerTruncateVecPack() local
20610 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, In); in LowerTruncateVecPack()
20882 MVT TruncVT = MVT::v4i1; in LowerFP_TO_INT() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 9763 EVT TruncVT = N->getValueType(0); in distributeTruncateThroughAnd() local
9765 TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { in distributeTruncateThroughAnd()
9770 SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00); in distributeTruncateThroughAnd()
9771 SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01); in distributeTruncateThroughAnd()
9774 return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01); in distributeTruncateThroughAnd()
10392 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue()); in visitSRA() local
10395 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorElementCount()); in visitSRA()
10405 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && in visitSRA()
10407 TLI.isTruncateFree(VT, TruncVT)) { in visitSRA()
10411 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, in visitSRA()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1682 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(), in PromoteIntRes_TRUNCATE() local
1684 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp); in PromoteIntRes_TRUNCATE()
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| H A D | LegalizeVectorTypes.cpp | 5982 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(), in convertMask()
5984 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask); in convertMask()
5978 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(), convertMask() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 923 virtual bool preferSextInRegOfTruncate(EVT TruncVT, EVT VT, EVT ExtVT) const { in preferSextInRegOfTruncate() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10207 EVT TruncVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); in widenLoad() local
10211 TruncVT = MemVT.changeTypeToInteger(); in widenLoad()
10217 DAG.getValueType(TruncVT)); in widenLoad()
10220 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5032 MVT TruncVT = MVT::getVectorVT(MVT::getIntegerVT(EltSize), NumElts); in skipExtensionForVectorMULL() local
5036 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N); in skipExtensionForVectorMULL()
5052 return DAG.getBuildVector(TruncVT, dl, Ops); in skipExtensionForVectorMULL()
27348 EVT TruncVT = ContainerVT.changeVectorElementType( in LowerFixedLengthVectorStoreToSVE() local
27351 NewValue = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, TruncVT, Pg, in LowerFixedLengthVectorStoreToSVE()
27353 DAG.getUNDEF(TruncVT)); in LowerFixedLengthVectorStoreToSVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9592 MVT TruncVT = MVT::getIntegerVT(EltSize); in SkipExtensionForVMULL() local
9601 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops); in SkipExtensionForVMULL()
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