| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 806 Register TrueReg = in simplifyCode() local
808 if (!TrueReg.isVirtual()) in simplifyCode()
810 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
873 Register TrueReg = in simplifyCode() local
875 if (!TrueReg.isVirtual()) in simplifyCode()
877 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
1222 Register TrueReg = in simplifyCode() local
1224 if (!TrueReg.isVirtual() || !MRI->hasOneNonDBGUse(TrueReg)) in simplifyCode()
1227 MachineInstr *SrcMI = MRI->getVRegDef(TrueReg); in simplifyCode()
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| H A D | PPCInstrInfo.cpp | 1522 Register DstReg, Register TrueReg, in canInsertSelect() argument
1544 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1569 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
1577 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1629 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1630 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3254 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3261 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3263 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3265 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
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| H A D | PPCInstrInfo.h | 452 ArrayRef<MachineOperand> Cond, Register TrueReg,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 789 auto TrueReg = MIB.getReg(2); in selectSelect() local
791 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
796 .addUse(TrueReg) in selectSelect()
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| H A D | ARMBaseInstrInfo.cpp | 2356 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
2359 const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg()); in optimizeSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 921 Register TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
922 if (TrueReg == 0) in selectSelect()
930 std::swap(TrueReg, FalseReg); in selectSelect()
972 .addReg(TrueReg) in selectSelect()
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| H A D | WebAssemblyISelLowering.cpp | 503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
509 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
543 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
547 .addReg(TrueReg) in LowerFPToInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 255 ArrayRef<MachineOperand> Cond, Register TrueReg,
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| H A D | SystemZInstrInfo.cpp | 552 Register DstReg, Register TrueReg, in canInsertSelect() argument
565 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
588 Register TrueReg, in insertSelect() argument
608 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
610 TrueReg = TReg; in insertSelect()
622 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
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| H A D | SystemZISelLowering.cpp | 8256 Register TrueReg = MI->getOperand(1).getReg(); in createPHIsForSelects() local
8263 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
8265 if (RegRewriteTable.contains(TrueReg)) in createPHIsForSelects()
8266 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
8273 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
8277 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 367 Register TrueReg, Register FalseReg, int &CondCycles,
373 Register TrueReg, Register FalseReg) const override;
378 Register TrueReg, Register FalseReg) const;
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| H A D | SIInstrInfo.cpp | 1230 Register TrueReg, in insertVectorSelect() argument
1246 .addReg(TrueReg) in insertVectorSelect()
1261 .addReg(TrueReg) in insertVectorSelect()
1275 .addReg(TrueReg) in insertVectorSelect()
1289 .addReg(TrueReg) in insertVectorSelect()
1301 .addReg(TrueReg) in insertVectorSelect()
1321 .addReg(TrueReg) in insertVectorSelect()
1339 .addReg(TrueReg) in insertVectorSelect()
3223 Register DstReg, Register TrueReg, in canInsertSelect() argument
3230 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 936 Register TrueReg, Register FalseReg, in canInsertSelect() argument
960 Register TrueReg, Register FalseReg) const { in insertSelect() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 417 ArrayRef<MachineOperand> Cond, Register TrueReg,
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| H A D | X86InstrInfo.cpp | 4099 Register DstReg, Register TrueReg, in canInsertSelect() argument
4114 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4137 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
4148 .addReg(TrueReg) in insertSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 404 ArrayRef<MachineOperand> Cond, Register TrueReg,
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| H A D | AArch64InstrInfo.cpp | 704 Register DstReg, Register TrueReg, in canInsertSelect() argument
711 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
731 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
755 Register TrueReg, Register FalseReg) const { in insertSelect() argument
858 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
863 TrueReg = FalseReg; in insertSelect()
877 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
882 .addReg(TrueReg) in insertSelect()
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