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Searched refs:TrueReg (Results 1 – 19 of 19) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperCasts.cpp212 Register TrueReg = Select->getTrueReg(); in matchCastOfSelect() local
214 LLT SrcTy = MRI.getType(TrueReg); in matchCastOfSelect()
224 auto True = B.buildInstr(Cast->getOpcode(), {DstTy}, {TrueReg}); in matchCastOfSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp801 Register TrueReg = in simplifyCode() local
803 if (!TrueReg.isVirtual()) in simplifyCode()
805 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
868 Register TrueReg = in simplifyCode() local
870 if (!TrueReg.isVirtual()) in simplifyCode()
872 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
1226 Register TrueReg = in simplifyCode() local
1228 if (!TrueReg.isVirtual() || !MRI->hasOneNonDBGUse(TrueReg)) in simplifyCode()
1231 MachineInstr *SrcMI = MRI->getVRegDef(TrueReg); in simplifyCode()
H A DPPCInstrInfo.cpp1520 Register DstReg, Register TrueReg, in canInsertSelect() argument
1542 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1567 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
1575 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1627 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1628 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3285 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3292 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3294 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3296 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h562 ArrayRef<MachineOperand> Cond, Register TrueReg,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp723 Register TrueReg = MI.getOperand(3).getReg(); in foldVMergeToMask() local
724 if (!TrueReg.isVirtual() || !MRI->hasOneUse(TrueReg)) in foldVMergeToMask()
726 MachineInstr &True = *MRI->getUniqueVRegDef(TrueReg); in foldVMergeToMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp789 auto TrueReg = MIB.getReg(2); in selectSelect() local
791 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
796 .addUse(TrueReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2199 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
2202 const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg()); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp927 Register TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
928 if (TrueReg == 0) in selectSelect()
936 std::swap(TrueReg, FalseReg); in selectSelect()
978 .addReg(TrueReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp550 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
556 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
590 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
594 .addReg(TrueReg) in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h259 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DSystemZInstrInfo.cpp600 Register DstReg, Register TrueReg, in canInsertSelect() argument
613 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
636 Register TrueReg, in insertSelect() argument
656 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
658 TrueReg = TReg; in insertSelect()
670 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZISelLowering.cpp9580 Register TrueReg = MI->getOperand(1).getReg(); in createPHIsForSelects() local
9587 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
9589 if (auto It = RegRewriteTable.find(TrueReg); It != RegRewriteTable.end()) in createPHIsForSelects()
9590 TrueReg = It->second.first; in createPHIsForSelects()
9597 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
9601 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h377 Register TrueReg, Register FalseReg, int &CondCycles,
383 Register TrueReg, Register FalseReg) const override;
388 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1192 Register TrueReg, in insertVectorSelect() argument
1207 .addReg(TrueReg) in insertVectorSelect()
1222 .addReg(TrueReg) in insertVectorSelect()
1236 .addReg(TrueReg) in insertVectorSelect()
1250 .addReg(TrueReg) in insertVectorSelect()
1262 .addReg(TrueReg) in insertVectorSelect()
1282 .addReg(TrueReg) in insertVectorSelect()
1300 .addReg(TrueReg) in insertVectorSelect()
3284 Register DstReg, Register TrueReg, in canInsertSelect() argument
3291 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h959 Register TrueReg, Register FalseReg, in canInsertSelect() argument
983 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h465 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DX86InstrInfo.cpp4158 Register DstReg, Register TrueReg, in canInsertSelect() argument
4173 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4196 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
4207 .addReg(TrueReg) in insertSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h410 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DAArch64InstrInfo.cpp764 Register DstReg, Register TrueReg, in canInsertSelect() argument
771 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
791 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
815 Register TrueReg, Register FalseReg) const { in insertSelect() argument
960 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
965 TrueReg = FalseReg; in insertSelect()
979 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
984 .addReg(TrueReg) in insertSelect()