Searched refs:TopDown (Results 1 – 11 of 11) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/ |
| H A D | PtrState.cpp | 59 static Sequence MergeSeqs(Sequence A, Sequence B, bool TopDown) { in MergeSeqs() argument
68 if (TopDown) { in MergeSeqs()
147 void PtrState::Merge(const PtrState &Other, bool TopDown) { in Merge() argument
148 Seq = MergeSeqs(GetSeq(), Other.GetSeq(), TopDown); in Merge()
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| H A D | PtrState.h | 155 void Merge(const PtrState &Other, bool TopDown);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVProcessors.td | 14 defvar TopDown = [{ MISched::TopDown }];
47 code PostRASchedDirection = TopDown;
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| H A D | RISCVSubtarget.cpp | 237 if (PostRASchedDirection == MISched::TopDown) { in overridePostRASchedPolicy()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 196 TopDown, enumerator
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| H A D | MachinePipeliner.h | 306 enum OrderKind { BottomUp = 0, TopDown = 1 }; enumerator
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| H A D | MachineScheduler.h | 112 TopDown, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 186 clEnumValN(MISched::TopDown, "topdown",
198 clEnumValN(MISched::TopDown, "topdown",
1034 D = ScheduleDAGMI::DumpDirection::TopDown; in enterRegion()
1404 if (DumpDir == DumpDirection::TopDown) in dumpSchedule()
3736 if (PreRADirection == MISched::TopDown) { in initPolicy()
4344 if (PostRADirection == MISched::TopDown) { in initPolicy()
4803 PreRADirection != MISched::TopDown && PreRADirection != MISched::BottomUp; in createInstructionShuffler()
4804 bool TopDown = PreRADirection != MISched::BottomUp; in createInstructionShuffler() local
4806 C, std::make_unique<InstructionShuffler>(Alternate, TopDown)); in createInstructionShuffler()
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| H A D | MachinePipeliner.cpp | 2509 Order = TopDown; in computeNodeOrder()
2514 Order = TopDown; in computeNodeOrder()
2536 if (Order == TopDown) { in computeNodeOrder()
2609 Order = TopDown; in computeNodeOrder()
2638 Order = TopDown; in computeNodeOrder()
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| H A D | VLIWMachineScheduler.cpp | 954 if (PreRADirection == MISched::TopDown) { in pickNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 252 bool TopDown; member in __anonbc27dab50111::Transformation
254 Transformation(bool TD) : TopDown(TD) {} in Transformation()
274 if (T.TopDown) in INITIALIZE_PASS_DEPENDENCY()
286 if (!T.TopDown) in INITIALIZE_PASS_DEPENDENCY()
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