Searched refs:TmpReg1 (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2163 Register TmpReg1 = PPCMaterialize32BitInt(Imm, RC); in PPCMaterialize64BitInt() local 2165 return TmpReg1; in PPCMaterialize64BitInt() 2173 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift); in PPCMaterialize64BitInt() 2175 TmpReg2 = TmpReg1; in PPCMaterialize64BitInt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2498 Register TmpReg1 = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local 2517 auto And = BuildMI(*MBB, I, DL, TII.get(AndOpc), TmpReg1) in selectG_TRUNC() 2522 .addReg(TmpReg1); in selectG_TRUNC() 6528 Register TmpReg1 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectNamedBarrierInit() local 6529 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_AND_B32), TmpReg1) in selectNamedBarrierInit() 6550 .addReg(TmpReg1) in selectNamedBarrierInit() 6583 Register TmpReg1 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectNamedBarrierInst() local 6584 BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_AND_B32), TmpReg1) in selectNamedBarrierInst() 6590 .addReg(TmpReg1); in selectNamedBarrierInst()
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| H A D | AMDGPURegisterBankInfo.cpp | 1883 Register TmpReg1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in buildVCopy() local 1889 .addDef(TmpReg1) in buildVCopy() 1895 .addUse(TmpReg1) in buildVCopy() 2953 Register TmpReg1 = MRI.createGenericVirtualRegister(S32); in applyMappingImpl() local 2955 MRI.setRegBank(TmpReg1, AMDGPU::SGPRRegBank); in applyMappingImpl() 2958 Extract1->getOperand(0).setReg(TmpReg1); in applyMappingImpl() 2963 buildVCopy(B, DstRegs[1], TmpReg1); in applyMappingImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2587 Register TmpReg1 = createResultReg(&AArch64::GPR32RegClass); in selectCmp() local 2589 TmpReg1) in selectCmp() 2595 .addReg(TmpReg1, getKillRegState(true)) in selectCmp()
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