| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | IntrinsicLowering.cpp | 97 Value *Tmp5 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
118 Tmp5 = Builder.CreateAnd(Tmp5, in LowerBSWAP()
135 Tmp6 = Builder.CreateOr(Tmp6, Tmp5, "bswap.or2"); in LowerBSWAP()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 289 Value *Tmp5 = Builder.CreateShl(R_1, One); in generateUnsignedDivisionCode() local
291 Value *Tmp7 = Builder.CreateOr(Tmp5, Tmp6); in generateUnsignedDivisionCode()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprComplex.cpp | 1096 llvm::Value *Tmp5 = Builder.CreateMul(RHSi, RHSi); // d*d in EmitBinDiv() local
1097 llvm::Value *Tmp6 = Builder.CreateAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8930 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
8950 Tmp5 = DAG.getNode(ISD::VP_ADD, dl, VT, Op, Tmp4, Mask, VL); in expandVPCTPOP()
8951 Op = DAG.getNode(ISD::VP_AND, dl, VT, Tmp5, Mask0F, Mask, VL); in expandVPCTPOP()
9370 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9396 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Op, in expandBSWAP()
9398 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Tmp5, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
9410 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); in expandBSWAP()
9430 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandVPBSWAP() local
9467 Tmp5 = DAG.getNode(ISD::VP_AND, dl, VT, Op, in expandVPBSWAP()
9469 Tmp5 = DAG.getNode(ISD::VP_SHL, dl, VT, Tmp5, DAG.getConstant(8, dl, SHVT), in expandVPBSWAP()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2471 SDValue Tmp5 = DAG.getNode(ShRight, dl, IntTy, {Tmp3, One}); in emitHvxShiftRightRnd()
2472 SDValue Mux = DAG.getNode(ISD::VSELECT, dl, IntTy, {Eq, Tmp5, Tmp4}); in emitHvxShiftRightRnd() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9120 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSHL_PARTS() local
9122 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); in LowerSHL_PARTS()
9149 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSRL_PARTS() local
9151 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); in LowerSRL_PARTS()
9177 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSRA_PARTS() local
9179 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); in LowerSRA_PARTS()
9181 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT), in LowerSRA_PARTS()
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