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Searched refs:Tmp4 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp71 Value *Tmp4 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
85 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
99 Value* Tmp4 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
122 Tmp4 = Builder.CreateAnd(Tmp4, in LowerBSWAP()
136 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
139 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
140 V = Builder.CreateOr(Tmp8, Tmp4, "bswap.i64"); in LowerBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp129 Value *Tmp4 = Builder.CreateXor(Q_Mag, Q_Sgn); in generateSignedDivisionCode() local
130 Value *Q = Builder.CreateSub(Tmp4, Q_Sgn); in generateSignedDivisionCode()
263 Value *Tmp4 = Builder.CreateAdd(Divisor, NegOne); in generateUnsignedDivisionCode() local
294 Value *Tmp9 = Builder.CreateSub(Tmp4, Tmp7); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4256 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4257 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4259 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4293 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4294 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4295 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4326 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4327 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4328 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4619 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp3088 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
4309 Tmp4 = Node->getOperand(3); // False in ExpandNode()
4325 DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4, Node->getFlags())); in ExpandNode()
4338 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC); in ExpandNode()
4348 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC); in ExpandNode()
4363 std::swap(Tmp3, Tmp4); in ExpandNode()
4369 Tmp1, Tmp2, Tmp3, Tmp4, CC); in ExpandNode()
4374 Tmp2, Tmp3, Tmp4, CC); in ExpandNode()
4387 Tmp4 = Node->getOperand(1); // CC in ExpandNode()
4390 DAG, getSetCCResultType(Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, in ExpandNode()
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H A DTargetLowering.cpp9335 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
9353 Tmp4 = DAG.getNode(ISD::VP_SRL, dl, VT, Op, DAG.getConstant(4, dl, ShVT), in expandVPCTPOP()
9355 Tmp5 = DAG.getNode(ISD::VP_ADD, dl, VT, Op, Tmp4, Mask, VL); in expandVPCTPOP()
9865 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9873 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9880 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in expandBSWAP()
9882 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); in expandBSWAP()
9894 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
9895 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, in expandBSWAP()
9906 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in expandBSWAP()
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1095 llvm::Value *Tmp4 = Builder.CreateMul(RHSr, RHSr); // c*c in EmitBinDiv() local
1097 llvm::Value *Tmp6 = Builder.CreateAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2507 SDValue Tmp4 = DAG.getNode(ShRight, dl, IntTy, {Tmp2, One}); in emitHvxShiftRightRnd() local
2509 SDValue Mux = DAG.getNode(ISD::VSELECT, dl, IntTy, {Eq, Tmp5, Tmp4}); in emitHvxShiftRightRnd()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9265 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS() local
9269 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSHL_PARTS()
9294 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS() local
9298 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSRL_PARTS()
9322 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS() local
9328 Tmp4, Tmp6, ISD::SETLE); in LowerSRA_PARTS()